JOHN BRENNAN, MD
Medical Practice at 12 St, Weissport, PA

License number
Pennsylvania MD0584741
Category
Medical Practice
Type
Clinical Pathology/Laboratory Medicine
Address
Address 2
211 N 12Th St, Weissport, PA 18235
2 Meridian Blvd FL 3, Reading, PA 19610
Phone
(610) 377-7086
(866) 372-6660
(670) 372-3735 (Fax)

Personal information

See more information about JOHN BRENNAN at radaris.com
Name
Address
Phone
John Brennan, age 98
5214 Arrowhead Ln, Drexel Hill, PA 19026
(610) 789-8638
John Brennan
521 Militia Hill Rd, Southampton, PA 18966
(215) 357-4009
John Brennan
50 W Ridge St, Nanticoke, PA 18634
(570) 735-0779
John Brennan
532 Pine Line Dr, Pittsburgh, PA 15237
(412) 445-5920
John Brennan, age 59
52 N Loveland Ave, Kingston, PA 18704

Professional information

John Brennan Photo 1

John Brennan, Wyomissing PA

Specialties:
Pathologist
Address:
2 Meridian Blvd, Wyomissing, PA 19610
211 N 12Th St, Lehighton, PA 18235
Education:
Doctor of Medicine
Board certifications:
American Board of Pathology Certification in Clinical Pathology (Pathology), American Board of Pathology Sub-certificate in Cytopathology (Pathology)


John Brennan Photo 2

Semiconductor Device Configured For Reducing Post-Fabrication Damage

US Patent:
7214568, May 8, 2007
Filed:
Feb 6, 2004
Appl. No.:
10/773614
Inventors:
John M. Brennan - Wyomissing PA, US
Joseph Michael Freund - Fogelsville PA, US
Sujal Dipak Shah - Fogelsville PA, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H01L 21/00
US Classification:
438113, 257E21705
Abstract:
A semiconductor device includes an IC die configured to reduce post-fabrication damage to the device. The IC die is formed such that at least a portion of one or more perimeter edges of the die are beveled by an etching process. The semiconductor device may include a plurality of IC dies, at least one of the IC dies being separated from the semiconductor device by forming one or more v-shaped grooves in an upper surface of the device, the v-shaped grooves defining perimeter edges of the at least one IC die. A back surface of the semiconductor device is removed until at least a portion of the v-shaped grooves are exposed. When the IC die is separated from the semiconductor device in this manner, a sidewall of each of the v-shaped grooves forms a beveled perimeter edge of the separated IC die.


John Brennan Photo 3

Methods And Apparatus For Wire Bonding With Wire Length Adjustment In An Integrated Circuit

US Patent:
7443042, Oct 28, 2008
Filed:
Mar 21, 2006
Appl. No.:
11/385245
Inventors:
Timothy Brooks Bambridge - Pittstown NJ, US
John Wayne Bowen - Warminster PA, US
John McKenna Brennan - Wyomissing PA, US
Joseph Michael Freund - Fogelsville PA, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H01L 23/48, H01L 23/52
US Classification:
257784, 257723, 257724
Abstract:
An integrated circuit is wire bonded in a manner such that there is consistent RF performance from integrated circuit package to integrated circuit package. Bond distances within the integrated circuit are measured, each corresponding to a wire bond to be formed. An area under a hypothetical wire bond profile is calculated as a function of the bond distances, a baseline wire length, and a baseline loop height. A wire is bonded across a given one of the bond distances to form a given one of the wire bonds. A wire bond profile for the given wire bond is provided having an area thereunder that is substantially equal to the calculated area.


John Brennan Photo 4

Semiconductor Packaging Techniques For Use With Non-Ceramic Packages

US Patent:
7075174, Jul 11, 2006
Filed:
Feb 26, 2004
Appl. No.:
10/788162
Inventors:
John McKenna Brennan - Wyomissing PA, US
Joseph Michael Freund - Fogelsville PA, US
Curtis James Miller - West Lawn PA, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H01L 23/495
US Classification:
257675, 257712, 257E23031, 257E23051, 257E23052
Abstract:
A method for attaching at least one IC die to a non-ceramic IC package including a leadframe and a base, the IC package being configured for receiving the at least one IC die, includes attaching the IC die to an upper surface of a thermal carrier in a manner which facilitates thermal transfer between the die and the carrier. The method further includes attaching the thermal carrier having the IC die attached thereto to an upper surface of the base of the IC package. In this manner, one or more IC dies may be attached to a standard plastic IC package without a significant impact on thermal transfer in the device and at a significant cost savings compared to ceramic IC packages.


John Brennan Photo 5

Integrated Circuit With Substantially Perpendicular Wire Bonds

US Patent:
7109589, Sep 19, 2006
Filed:
Aug 26, 2004
Appl. No.:
10/926631
Inventors:
John M. Brennan - Wyomissing PA, US
Donald Farrell - Allentown PA, US
Joseph Michael Freund - Fogelsville PA, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H01L 23/52, H01L 23/48, H01L 29/40
US Classification:
257784, 257531, 257779, 257780, 257781, 257786, 361704, 361707, 2281805
Abstract:
An integrated circuit comprises an integrated circuit package and a plurality of circuit elements disposed within the integrated circuit package. A plurality of wire bonds provide connections for at least one of the circuit elements. At least one wire bond in a first subset of wire bonds and at least one wire bond in a second subset of wire bonds are substantially perpendicular to one another at a crossing point of the wire bonds in a plan view of the integrated circuit.


John Brennan Photo 6

Methods And Apparatus For Wire Bonding With Wire Length Adjustment In An Integrated Circuit

US Patent:
7086148, Aug 8, 2006
Filed:
Feb 25, 2004
Appl. No.:
10/787010
Inventors:
Timothy Brooks Bambridge - Pittstown NJ, US
John Wayne Bowen - Warminster PA, US
John McKenna Brennan - Wyomissing PA, US
Joseph Michael Freund - Fogelsville PA, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H05K 3/00
US Classification:
29843, 29842, 29850, 228 45, 228179, 2281805
Abstract:
An integrated circuit is wire bonded in a manner such that there is consistent RF performance from integrated circuit package to integrated circuit package. Bond distances within the integrated circuit are measured, each corresponding to a wire bond to be formed. An area under a hypothetical wire bond profile is calculated as a function of the bond distances, a baseline wire length, and a baseline loop height. A wire is bonded across a given one of the bond distances to form a given one of the wire bonds. A wire bond profile for the given wire bond is provided having an area thereunder that is substantially equal to the calculated area.


John Brennan Photo 7

Integrated Circuit With Substantially Perpendicular Wire Bonds

US Patent:
7465655, Dec 16, 2008
Filed:
Jul 27, 2006
Appl. No.:
11/494221
Inventors:
John M. Brennan - Wyomissing PA, US
Donald Farrell - Allentown PA, US
Joseph Michael Freund - Fogelsville PA, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H01L 21/44, B23K 37/00
US Classification:
438617, 257E21506, 228 45
Abstract:
A method for performing a wire-bonding operation in an integrated circuit utilizes a bonding tool. A wire is bonded to a first bond site in the integrated circuit, and terminated at a second bond site in the integrated circuit. The bonding and terminating steps are repeated for a plurality of additional wire bonds of the integrated circuit. At least two wire bonds in the integrated circuit are substantially perpendicular to one another at a crossing point in a plan view of the integrated circuit.


John Brennan Photo 8

Methods And Apparatus For Wire Bonding With Wire Length Adjustment In An Integrated Circuit

US Patent:
7637414, Dec 29, 2009
Filed:
Jul 11, 2008
Appl. No.:
12/171903
Inventors:
Timothy Brooks Bambridge - Pittstown NJ, US
John Wayne Bowen - Warminster PA, US
John McKenna Brennan - Wyomissing PA, US
Joseph Michael Freund - Fogelsville PA, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
B23K 31/00
US Classification:
2281805, 228 45, 228103
Abstract:
An integrated circuit is wire bonded in a manner such that there is consistent RF performance from integrated circuit package to integrated circuit package. Bond distances within the integrated circuit are measured, each corresponding to a wire bond to be formed. An area under a hypothetical wire bond profile is calculated as a function of the bond distances, a baseline wire length, and a baseline loop height. A wire is bonded across a given one of the bond distances to form a given one of the wire bonds. A wire bond profile for the given wire bond is provided having an area thereunder that is substantially equal to the calculated area.


John Brennan Photo 9

Techniques For Reducing Bowing In Power Transistor Devices

US Patent:
7164200, Jan 16, 2007
Filed:
Feb 27, 2004
Appl. No.:
10/788678
Inventors:
John McKenna Brennan - Wyomissing PA, US
Joseph Michael Freund - Fogelsville PA, US
John William Osenbach - Kutztown PA, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H01L 23/10, H01L 23/34
US Classification:
257707, 257728
Abstract:
Power transistor devices and techniques for reducing bowing in such devices are provided. In one aspect, a power transistor device is provided. The power transistor device comprises a substrate, a device film formed on the substrate and an adhesion layer formed on a side of the substrate opposite the device film, wherein at least a portion of the adhesion layer is at least partially segmented. The power transistor device thereby exhibits a reduced amount of bowing relative to an amount of bowing expected without the segmenting of the adhesion layer. The power transistor device may be part of an integrated circuit.


John Brennan Photo 10

Semiconductor Device With Improved Thermal Characteristics

US Patent:
2005018, Aug 25, 2005
Filed:
Feb 23, 2004
Appl. No.:
10/784756
Inventors:
John Brennan - Wyomissing PA, US
Joseph Freund - Fogelsville PA, US
Sujal Shah - Fogelsville PA, US
Richard Shanaman - Richland PA, US
International Classification:
H01L023/10
US Classification:
257706000
Abstract:
A semiconductor device includes a substrate and an active region formed in the substrate proximate an upper surface of the substrate. The active region includes at least one circuit element formed therein. At least one channel is formed in a back surface of the substrate opposite the upper surface of the substrate, the channel being formed proximate the active region. The channel is substantially filled with one or more layers of a thermally conductive material and configured so as to provide a thermal conduction path for conducting heat away from the active region.