DR. JOEL T DAVIDSON, MD
Anesthesiologist Assistant at Medical Pkwy, Austin, TX

6550002, Apr 15, 2003

Nov 4, 1999

09/435067

Joel Roger Davidson - Austin TX
Hung Oui Le - Austin TX
Alexander Erik Mericas - Austin TX

International Business Machines Corporation - Armonk NY

G06F 1130

712216, 714 38

A method and system for detecting flushed instructions without a flush indicator is provided. In order to monitor the flushing of an instruction in an instruction pipeline of a processor, an instruction is selected as a sampled instruction and the progress of the sampled instruction through the instruction pipeline is monitored. Upon selection of an instruction as a sampled instruction, a countdown value is initialized to a value equal to the maximum number of instructions within the instruction pipeline, and as instructions complete, the countdown value is decremented. If progress of the sampled instruction is detected as the instruction moves through the instruction pipeline, the countdown value is reinitialized. If the countdown value reaches zero, then a flush of the sampled instruction from the instruction pipeline is presumed, and an indication that the sampled instruction has been flushed is generated. In response to the indication that the sampled instruction has been flushed, a subsequent instruction may be selected as a subsequently sampled instruction.

6574727, Jun 3, 2003

Nov 4, 1999

09/435069

Joel Roger Davidson - Austin TX
John Edward Derrick - Round Rock TX
Alexander Erik Mericas - Austin TX

International Business Machines Corporation - Armonk NY

G06F 900

712227, 703 22

A method and apparatus for selecting an instruction to be monitored within a pipelined processor in a data processing system is presented. A plurality of instructions are fetched, and the plurality of instructions are matched against at least one match condition to generate instructions that are eligible for sampling. The match conditions may include matching the opcode of an instruction, the pre-decode bits of an instruction, a type of instruction, or other conditions. The matched instructions may be marked using a match bit that accompanies the instruction through the selection process. The instructions eligible for sampling are then sampled to generate a sampled instruction. A sampled instruction may be marked with a sample bit that accompanies the instruction through the instruction execution process in order to monitor the sampled instruction while it is executing within the pipelined processor.

6804692, Oct 12, 2004

Dec 21, 2001

10/037082

Joel R. Davidson - Austin TX
James T. Kirk - Austin TX
Mauricio Calle - Austin TX

Agere Systems, Inc. - Allentown PA

G06F 700

7077041, 700101, 700 1, 700 10

A method and apparatus for reassembling data blocks back into their constituent data packets in a network processor. Each data block associated with a packet is assigned a unique queue identifier for use in assembling all blocks from the same packet. The packet is also assigned a packet identifier, a start of packet identifier and an end of packet identifier for use by downstream network processors to process the packet. The blocks are assembled according to the assigned queue identifier until the last block of a packet is received, at which time the packet reassembly is complete.

2003012, Jun 26, 2003

Dec 21, 2001

10/029679

Gregg Bouchard - Round Rock TX, US
Mauricio Calle - Austin TX, US
Joel Davidson - Austin TX, US
Michael Hathaway - Austin TX, US
James Kirk - Austin TX, US
Christopher Walton - Austin TX, US

G06F015/16

709/236000, 709/214000, 709/250000

A packet processing system comprises first processing circuitry for performing a first function, and first memory circuitry coupled to the first processing circuitry for storing received packets, wherein at least a portion of the packets stored by the first memory circuitry are usable by the first processing circuitry in accordance with the first function. The packet processing system further comprises at least second processing circuitry for performing a second function, and at least second memory circuitry coupled to the second processing circuitry for storing at least a portion of the same packets stored in the first memory circuitry, wherein at least a portion of the packets stored in the second memory circuitry are usable by the second processing circuitry in accordance with the second function. In an illustrative embodiment, the first processing circuitry and the second processing circuitry operate in a packet switching device such as a router. In such case, the first processing circuitry and the second processing circuitry operate between a packet network interface and a switch fabric of the packet switching device.

7113518, Sep 26, 2006

Dec 19, 2001

10/025352

Mauricio Calle - Austin TX, US
Joel R. Davidson - Austin TX, US
Michael W. Hathaway - Austin TX, US
James T. Kirk - Austin TX, US

Agere Systems Inc. - Allentown PA

H04L 12/56, G06F 13/00, G06F 15/173

370412, 709238, 370392

A network processor or other type of processor includes a packet analyzer and first memory circuitry operatively coupled to the packet analyzer. The packet analyzer is operative to at least partially analyze one or more packets received by the processor in order to determine for a given one of the packets a portion of the packet to be stored in the first memory circuitry. The portion of the given packet when stored in the first memory circuitry is thereby made accessible for subsequent processing within the processor, without requiring access to second memory circuitry associated with the processor and configured to store substantially the entire given packet. The packet analyzer may be configured to utilize a value stored in a register of the processor to determine the portion of the given packet to be stored in the first memory circuitry. The register may be one of a number of registers which implement a look-up table accessible to the packet analyzer. The look-up table includes multiple entries, each having packet categorizing information, such as port number or packet flow identifier, and an associated number of blocks of the packet to be stored in the first memory circuitry.

7079539, Jul 18, 2006

Dec 21, 2001

10/029705

Mauricio Calle - Austin TX, US
Joel R. Davidson - Austin TX, US
Betty A. McDaniel - Austin TX, US

Agere Systems Inc. - Allentown PA

H04L 12/28, H04L 12/50, H04Q 11/00

370392, 370428

A network processor or other type of processor includes in an illustrative embodiment a first pass classifier coupled to first memory circuitry in the form of a relatively small internal memory, and a second pass classifier coupled to second memory circuitry in the form of a larger internal buffer memory. The first memory circuitry is configurable to store at least a portion of a given packet to be processed by the first pass classifier. The second memory circuitry is configurable to store a different and preferably smaller portion of the given packet to permit processing thereof by the second pass classifier. The portion of the given packet storable in the second memory circuitry is a portion of the given packet determined by a first pass classification, performed by the first pass classifier, to be required for a second pass classification, performed by the second pass classifier. Advantageously, the invention reduces the size of the packet portion required to be stored in the second memory circuitry, thereby reducing the required memory of the processor. The processor may be configured as a network processor integrated circuit to provide an interface between a network from which the packet is received and a switch fabric in a router or switch.

6915480, Jul 5, 2005

Dec 21, 2001

10/029704

Mauricio Calle - Austin TX, US
Joel R. Davidson - Austin TX, US
James T. Kirk - Austin TX, US
Betty A. McDaniel - Austin TX, US
Maurice A. Uebelhor - East Leander TX, US

Agere Systems Inc. - Allentown PA

H03M013/00, G06F011/00

714799, 714774

A network processor or other type of processor includes first classification circuitry, scheduling circuitry and second classification circuitry. The first classification circuitry is configured to determine for a given packet received by the processor whether the packet has one or more errors. The scheduling circuitry in an illustrative embodiment receives an indication of the error determination made by the first classification circuitry, and based on the indication controls the dropping of the given packet from the processor memories if the packet has one or more errors, e. g. , via a flush transmit command. The second classification circuitry, which may be implemented as a single classification engine or a set of such engines, may be configured to perform at least one classification operation for the given packet, e. g. , if the packet is supplied thereto by the scheduling circuitry.