JIAN LIN, LAC
Acupuncture at University Ave, San Diego, CA

6615341, Sep 2, 2003

Jun 5, 2001

09/876189

Gilbert C. Sih - San Diego CA
Qiuzhen Zou - La Jolla CA
Inyup Kang - San Diego CA
Quaeed Motiwala - San Diego CA
Deepu John - La Jolla CA
Li Zhang - San Diego CA
Haitao Zhang - La Jolla CA
Charles E. Sakamaki - San Diego CA
Prashant A. Kantak - San Diego CA
Sanjay K. Jha - San Diego CA
Jian Lin - San Diego CA

Qualcomm, Inc. - San Diego CA

G06F 9302

712221, 712222, 712 41, 712 33, 712 35, 712 25, 708495, 708204, 708501

A digital signal processor (DSP) employs a variable-length instruction set. A portion of the variable-length instructions may be stored in adjacent locations within memory space with the beginning and ending of instructions occurring across memory word boundaries. The instructions may contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation, or operations, to be performed allowing multiple operations during each clock cycle. The DSP includes multiple data buses, and in particular three data buses. The DSP may also use a register bank that has registers accessible by at least two processing units, allowing multiple operations to be performed on a particular set of data by the multiple processing units, without reading and writing the data to and from a memory. an instruction fetch unit that receives instructions of variable length stored in an instruction memory. An instruction memory may advantageously be separate from the three data memories.

6496920, Dec 17, 2002

Mar 18, 1998

09/044088

Qiuzhen Zou - San Diego CA 92126
Gilbert C. Sih - San Diego CA 92129
Jian Lin - San Diego CA 92126

G06F 900

712 33, 712 35

A method and circuit for digital signal processing. The disclosed method and circuit uses a variable length instruction set. A portion of the variable length instructions may be stored in adjacent locations within memory. The beginning and ending of instructions may occur across memory word boundaries. Instructions may contain variable numbers of instruction fragments that cause a particular operation to be performed. The disclosed circuit has a set of three data buses over which data may be exchanged with a register bank and three data memories. Data buses include one wide bus and two narrow buses. The wide bus is coupled to a wide data memory and the two narrow buses are coupled to two narrow data memories. Additionally, the disclosed circuit has a register bank that is accessible by at least two processing units. The disclosed circuit further includes an instruction fetch unit that receives instructions of variable length stored in an instruction memory.

7502911, Mar 10, 2009

Sep 25, 2006

11/535005

Gilbert C. Sih - San Diego CA, US
Qiuzhen Zou - San Diego CA, US
Jian Lin - San Diego CA, US

QUALCOMM Incorporated - San Diego CA

G06F 9/30

712210, 712205

A digital signal processor uses a variable length instruction set. The variable length instructions may be stored in adjacent locations within memory space. The beginning and ending of instructions may, but are not required to, occur across memory word boundaries. Preferably, the variable length instructions contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation (or operations) to be performed, thereby allowing multiple operations to be performed during each clock cycle. This reduces the total number of clock cycles necessary to perform a task.

6865656, Mar 8, 2005

Sep 10, 2001

09/950742

Simon Turner - San Diego CA, US
Scott King - Poway CA, US
Jian Lin - San Diego CA, US
Kerry Taylor - San Diego CA, US

Qualcomm Incorporated - San Diego CA

G06F012/00

711165, 711100, 711101, 711104, 711154, 709216

A method and system for transferring data bytes includes a first memory adapted to store a plurality of multiple-byte data words including header field bytes and one or more data field bytes. The system also includes a second memory adapted to store data field bytes transferred thereto from the first memory. A controller coupled to the first and second memories reads a data word including the header field byte and the one or more data field bytes out of the first memory. The system also includes a data packer coupled to the controller and the second memory. The controller and data packer cooperate to transfer the one or more data field bytes of the first data word read from the first memory to the second memory. The data packer stores only the one or more data field bytes in the second memory contiguously with a previously transferred and stored data field byte.

5854565, Dec 29, 1998

Jun 24, 1997

8/881555

Sanjay K. Jha - San Diego CA
Jian Lin - San Diego CA

Qualcomm Incorporated - San Diego CA

H03K 3289

327202

The present invention is a novel and improved method and apparatus for implementing a latch within an integrated circuit. Data is stored on a storage node via the application of either a first or second state logic source applied through a feedback inverter that maintains the storage node at a particular logic state. During logic transitions from a first state to a second state the storage node is decoupled from the first state logic source via the use of a gating circuit, and the new logic level is applied to the storage node. During logic transitions from the second state to the first state the storage node remains coupled to the second state logic source. The coupling and decoupling of the storage node from the first state logic source is performed via the use of a clock signal that has a non-overlapping cycle with respect to a second clock signal that is used to control the transitions of the state of the latch.

7450959, Nov 11, 2008

May 6, 2004

10/841739

Jian Lin - San Diego CA, US
Nicholas K. Yu - San Diego CA, US

QUALCOMM Incorporated - San Diego CA

H04M 1/00

4555501, 455410, 455557, 714 42, 726 17

Wireless mobile communication device includes unified memory portion; processing units coupled with, and communicating through, unified memory; fault inhibitor coupled with unified memory inhibiting operational fault from nocent informon. Memory, fault inhibitor, and processing units fabricated on monolithic integrated circuit as system-on-chip disposed in wireless mobile personal host. Multiprocessor module includes fault inhibitor and applications and communications processing units and buses, coupled with unified memory. Integrated functional constituent can include coprocessor, accelerator, operational control unit, interprocessor controller, memory controller, bus management unit, bridge, arbiters, and transceiver. Method inhibits operational fault from nocent informon, setting device in operational or fallback state.

7606266, Oct 20, 2009

May 10, 2006

11/431804

Nischal Abrol - San Diego CA, US
Jian Lin - San Diego CA, US
Hanfang Pan - San Diego CA, US
Simon Turner - San Diego CA, US

QUALCOMM Incorporated - San Diego CA

H04J 3/00

370476, 370470, 370472, 370522, 714757, 714758, 714776, 714781, 714807

An HDLC accelerator includes a deframer and framer to respectively accelerate the deframing and framing processes for PPP packets. The deframer includes an input interface unit, a detection unit, a conversion unit, and an output interface unit. The input interface unit receives a packet of data to be deframed. The detection unit evaluates each data byte to detect for special bytes (e. g. , flag, escape, and invalid bytes). The conversion unit deframes the received data by removing flag and escape bytes, “un-escaping” the data byte following each escape byte, providing a header word for each flag byte, and checking each deframed packet based on a frame check sequence (FCS) value associated with the packet. The output interface unit provides deframed data and may further perform byte alignment in providing the deframed data. A state control unit provides control signals indicative of specific tasks to be performed for deframing.

7729322, Jun 1, 2010

Feb 28, 2002

10/086576

Nischal Abrol - San Diego CA, US
Jian Lin - San Diego CA, US
Hanfang Pan - San Diego CA, US
Simon Turner - San Diego CA, US

QUALCOMM Incorporated - San Diego CA

H04W 4/00

370338, 370310, 370349, 370413, 370471

An HDLC accelerator includes a deframer and framer to respectively accelerate the deframing and framing processes for PPP packets. The deframer includes an input interface unit, a detection unit, a conversion unit, and an output interface unit. The input interface unit receives a packet of data to be deframed. The detection unit evaluates each data byte to detect for special bytes (e. g. , flag, escape, and invalid bytes). The conversion unit deframes the received data by removing flag and escape bytes, “un-escaping” the data byte following each escape byte, providing a header word for each flag byte, and checking each deframed packet based on a frame check sequence (FCS) value associated with the packet. The output interface unit provides deframed data and may further perform byte alignment in providing the deframed data. A state control unit provides control signals indicative of specific tasks to be performed for deframing.