JESSE ELDON THOMPSON, MD
Radiology in Los Angeles, CA

7534652, May 19, 2009

Dec 27, 2005

11/318846

Belgacem Haba - Saratoga CA, US
Ilyas Mohammed - Santa Clara CA, US
Craig S. Mitchell - San Jose CA, US
Michael Warner - San Jose CA, US
Jesse Burl Thompson - Brentwood CA, US

Tessera, Inc. - San Jose CA

H01L 21/44

438108, 438117, 438611

A dielectric structure is formed by a molding process, so that a first surface of a dielectric structure is shaped by contact with the mold. The opposite second surface of the dielectric structure is applied onto the front surface of a wafer element. The dielectric layer may include protruding bumps and terminals may be formed on the bumps. The bumps may be of a precise height. The terminals lie at a precisely controlled height above the front surface of the wafer element. The terminals may include projecting posts which extend above a surrounding solder mask layer to facilitate engagement with a test fixture. The posts are immersed within solder joints when the structure is bonded to a circuit panel.

2005018, Sep 1, 2005

Mar 1, 2005

11/068831

Giles Humpston - San Jose CA, US
Philip Osborn - Mountain View CA, US
Jesse Thompson - Brentwood CA, US
Yoichi Kubota - Pleasanton CA, US
Chung-Chuan Tseng - San Jose CA, US
Robert Burtzlaff - Santa Clara CA, US
Belgacem Haba - Cupertino CA, US
David Tuckerman - Orinda CA, US
Michael Warner - San Jose CA, US

Tessera, Inc. - San Jose CA

H01L023/495

257678000

Various embodiments of packaged chips and ways of fabricating them are disclosed herein. One such packaged chip disclosed herein includes a chip having a front face, a rear face opposite the front face, and a device at one of the front and rear faces, the device being operable as a transducer of at least one of acoustic energy and electromagnetic energy, and the chip including a plurality of bond pads exposed at one of the front and rear faces. The packaged chip includes a package element having a dielectric element and a metal layer disposed on the dielectric element, the package element having an inner surface facing the chip and an outer surface facing away from the chip. The metal layer includes a plurality of contacts exposed at at least one of the inner and outer surfaces, the contacts conductively connected to the bond pads. The metal layer further includes a first opening for passage of the at least one of acoustic energy and electromagnetic energy in a direction of at least one of to said device and from said device.

2005018, Sep 1, 2005

Mar 1, 2005

11/068830

Giles Humpston - San Jose CA, US
Philip Osborn - Mountain View CA, US
Jesse Thompson - Brentwood CA, US
Yoichi Kubota - Pleasanton CA, US
Chung-Chuan Tseng - San Jose CA, US
Robert Burtzlaff - Santa Clara CA, US
Belgacem Haba - Cupertino CA, US
David Tuckerman - Orinda CA, US
Michael Warner - San Jose CA, US

Tessera, Inc. - San Jose CA

H01L023/495

257659000

Various embodiments of packaged chips and ways of fabricating them are disclosed herein. One such packaged chip disclosed herein includes a chip having a front face, a rear face opposite the front face, and a device at one of the front and rear faces, the device being operable as a transducer of at least one of acoustic energy and electromagnetic energy, and the chip including a plurality of bond pads exposed at one of the front and rear faces. The packaged chip includes a package element having a dielectric element and a metal layer disposed on the dielectric element, the package element having an inner surface facing the chip and an outer surface facing away from the chip. The metal layer includes a plurality of contacts exposed at at least one of the inner and outer surfaces, the contacts conductively connected to the bond pads. The metal layer further includes a first opening for passage of the at least one of acoustic energy and electromagnetic energy in a direction of at least one of to said device and from said device.

7510401, Mar 31, 2009

Oct 12, 2006

11/546899

Giles Humpston - Aylesbury, GB
Jesse Burl Thompson - Brentwood CA, US

Tessera, Inc. - San Jose CA

H01R 12/00

439 66

A microelectronic component having a base and a plurality of conductive posts extending from said base. Each of the posts is formed from a connected lattice of metal having voids therein. The lattice may be formed by depositing metal onto a sacrificial element such as an open-celled polymeric foam. During use or during processing, the posts may be deformed , as by crushing the lattice.

2005015, Jul 14, 2005

Oct 20, 2004

10/969527

Jesse Thompson - Brentwood CA, US
Jennifer Alfonso - Santa Clara CA, US
Glenn Urbish - Coral Springs FL, US
Philip Osborn - Mountain View CA, US
Ellis Chau - San Jose CA, US

Tessera, Inc. - San Jose CA

B65D085/30

206710000, 206832000

A microelectronic fold package is formed from an in-process unit including an internal unit such as a chip and a tape defining a bottom run extending beneath the internal unit, a top run extending above the internal unit and a fold connecting said top and bottom runs. The in-process unit is engaged between a pair of elements having flat surfaces so that these elements form the top and bottom runs to a substantially flat condition at least in regions between the internal unit and the fold and so that the engagement elements form the fold to a height equal to the height of the internal unit.

2008028, Nov 27, 2008

Aug 5, 2008

12/186433

Jennifer BRANTLEY - Dublin CA, US
Kenneth NEWELL - Livermore CA, US
David SOPCHAK - Oakland CA, US
Ian W. KAYE - Livermore CA, US
Jesse THOMPSON - Brentwood CA, US
Arpad SOMOGYVARI - Livermore CA, US

ULTRACELL CORPORATION - Livermore CA

B21D 51/16, H01M 8/00

29890, 427115

A method for manufacturing a fuel processor may comprise coupling a plurality of micro-tubes in parallel to form a flow field tube array, each of the plurality of micro-tubes designed to receive a fluid flow, depositing a catalyst layer inside each of the plurality of micro-tubes, and attaching at least one burner to a first end of the flow field tube array.

7176043, Feb 13, 2007

Dec 16, 2004

11/014439

Belgacem Haba - Cupertino CA, US
Masud Beroz - Livermore CA, US
Ronald Green - San Jose CA, US
Ilyas Mohammed - Santa Clara CA, US
Stuart E. Wilson - Menlo Park CA, US
Wael Zohni - San Jose CA, US
Yoichi Kubota - Pleasanton CA, US
Jesse Burl Thompson - Brentwood CA, US

Tessera, Inc. - San Jose CA

H01L 21/66

438 14, 438 18

A microelectronic package includes a microelectronic element having faces and contacts and a flexible substrate spaced from and overlying a first face of the microelectronic element. The package also includes a plurality of conductive posts extending from the flexible substrate and projecting away from the first face of the microelectronic element, wherein at least some of the conductive posts are electrically interconnected with the microelectronic element, and a plurality of support elements supporting the flexible substrate over the microelectronic element. The conductive posts are offset from the support elements to facilitate flexure of the substrate and movement of the posts relative to the microelectronic element.

5466302, Nov 14, 1995

May 9, 1994

8/239866

Paul G. Carey - Mountain View CA
Jesse B. Thompson - Brentwood CA
Nicolas J. Colella - Livermore CA
Kenneth A. Williams - Livermore CA

Regents of the University of California - Oakland CA

H01L 3105, H01L 3118

136251

Electrical interconnects for solar cells or other electronic components using a silver-silicone paste or a lead-tin (Pb-Sn) no-clean fluxless solder cream, whereby the high breakage of thin (<6 mil thick) solar cells using conventional solder interconnect is eliminated. The interconnects of this invention employs copper strips which are secured to the solar cells by a silver-silicone conductive paste which can be used at room temperature, or by a Pb-Sn solder cream which eliminates undesired residue on the active surfaces of the solar cells. Electrical testing using the interconnects of this invention has shown that no degradation of the interconnects developed under high current testing, while providing a very low contact resistance value.

2012012, May 24, 2012

Aug 8, 2008

12/673192

Jason A.A. West - Pleasanton CA, US
Jesse Thompson - Brentwood CA, US

ARCXIS Biotechnologies - Pleasanton CA

G01N 30/00, B29C 59/02, B29C 45/00, B32B 37/06, B29C 45/03, B29C 45/73, B01L 3/00, B05D 5/00

422430, 422502, 422 681, 264293, 427275, 427243, 1562722, 425542, 425547, 2643281

Provided are microfluidic devices and methods for fabricating and bonding such devices. Also provided are kits for analyzing analyte-containing samples and for lysing cells.