JEFFRY ROBIN GALLANT
Pilots at Toboggan Run, Midland, MI
License number
Michigan A5084637
Issued Date
Aug 2016
Expiration Date
Aug 2018
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
3002 Toboggan Run, Midland, MI 48642
Personal information
See more information about JEFFRY ROBIN GALLANT at radaris.comName
Address
Phone
413 Wanetah Dr, Midland, MI 48640
3002 Toboggan Run, Midland, MI 48642
413 Wanetah Dr, Midland, MI 48640
Professional information
See more information about JEFFRY ROBIN GALLANT at trustoria.com
Massively Multiplexed Superscalar Harvard Architecture Computer
Massively Multiplexed Superscalar Harvard Architecture Computer
US Patent:
5655133, Aug 5, 1997
Filed:
Nov 13, 1995
Appl. No.:
8/558921
Inventors:
Wayne P. Dupree - Midland MI
Stephen G. Churchill - Midland MI
Jeffry R. Gallant - Midland MI
Larry A. Root - Midland MI
William J. Bressette - Saginaw MI
Robert A. Orr - Midland MI
Srikala Ramaswamy - Midland MI
Jeffrey A. Lucas - Midland MI
James A. Bleck - Midland MI
Stephen G. Churchill - Midland MI
Jeffry R. Gallant - Midland MI
Larry A. Root - Midland MI
William J. Bressette - Saginaw MI
Robert A. Orr - Midland MI
Srikala Ramaswamy - Midland MI
Jeffrey A. Lucas - Midland MI
James A. Bleck - Midland MI
Assignee:
The Dow Chemical Company - Midland MI
International Classification:
G06F 930
US Classification:
39580023
Abstract:
A massively multiplexed central processing unit ("CPU") which has a plurality of independent computational circuits, a separate internal result bus for transmitting the resultant output from each of these computational circuits, and a plurality of general purpose registers coupled to each of the computational circuits. Each of the general purpose registers have multiplexed input ports which are connected to each of the result buses. Each of the general purpose registers also have an output port which is connected to a multiplexed input port of at least one of the computational circuits. Each of the computational circuits are dedicated to at least one unique mathematical function, and at least one of the computational circuits include at least one logical function. At least one of the computational circuits includes a plurality of concurrently operable mathematical and logical processing circuits, and an output multiplexer for selecting one of the resultant outputs for transmission on its result bus. The CPU also features a very long instruction word which uses a series of assigned bit locations to represent the selections codes for each of the CPU components.