JEFFREY PAUL BONN
Pilots at Sherwood Sq, Essex Junction, VT
License number
Vermont A5131707
Issued Date
Jun 2015
Expiration Date
Jun 2017
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
321 Sherwood Sq, Essex Junction, VT 05452
Personal information
See more information about JEFFREY PAUL BONN at radaris.comName
Address
Phone
321 Sherwood Sq, Essex Junction, VT 05452
321 Sherwood Sq, Essex Junction, VT 05452
Essex Junction, VT
Professional information
Integrated Circuit And Design Structure Having Reduced Through Silicon Via-Induced Stress
US Patent:
2012018, Jul 19, 2012
Filed:
Jan 13, 2011
Appl. No.:
13/005883
Inventors:
Jeffrey P. Bonn - Essex Junction VT, US
Brent A. Goplen - Underhill VT, US
Brian L. Kinsman - Essex Junction VT, US
Robert M. Rassel - Colchester VT, US
Edmund J. Sprogis - Williston VT, US
Daniel S. Vanslette - Fairfax VT, US
Brent A. Goplen - Underhill VT, US
Brian L. Kinsman - Essex Junction VT, US
Robert M. Rassel - Colchester VT, US
Edmund J. Sprogis - Williston VT, US
Daniel S. Vanslette - Fairfax VT, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
H01L 23/48, G06F 17/50
US Classification:
257774, 716119, 716100, 257E23011
Abstract:
Embodiments of the invention provide an integrated circuit (IC) having reduced through silicon via (TSV)-induced stresses and related IC design structures and methods. In one embodiment, the invention includes a method of designing an integrated circuit (IC) having reduced substrate stress, the method including: placing in an IC design file a plurality of through silicon via (TSV) placeholder cells, each placeholder cell having an undefined TSV orientation; replacing a first portion of the plurality of TSV placeholder cells with a first group of TSV cells having a first orientation; and replacing a second portion of the plurality of TSV placeholder cells with a second group of TSV cells having a second orientation substantially perpendicular to the first orientation, wherein TSV cells having the first orientation and TSV cells having the second orientation are interspersed to reduce a TSV-induced stress in an IC substrate.
Aspect Ratio Program For Optimizing Semiconductor Chip Shape
US Patent:
6021267, Feb 1, 2000
Filed:
Sep 8, 1997
Appl. No.:
8/925513
Inventors:
Jeffrey P. Bonn - Essex Junction VT
Daniel N. Maynard - Craftsbury Common VT
Sharon B. Sisler - Waterbury Center VT
Richard C. Whiteside - Charlotte VT
Daniel N. Maynard - Craftsbury Common VT
Sharon B. Sisler - Waterbury Center VT
Richard C. Whiteside - Charlotte VT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1750
US Classification:
39550022
Abstract:
A cost-based algorithm determines semiconductor chip aspect ratios which minimize lithographic processing costs and determines optimum chip matrices for various types of lithographic tools.