JEFFREY MICHAEL KLAAS
Pilots in Austin, TX

License number
Texas A1028522
Issued Date
Aug 2015
Expiration Date
Aug 2017
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
117 Blue Jay Ct, Austin, TX 78734

Professional information

Jeffrey Klaas Photo 1

Systems And Methods For Controlling Audio Volume In The Processor Of A High Definition Audio Codec

US Patent:
8224469, Jul 17, 2012
Filed:
Sep 1, 2008
Appl. No.:
12/202355
Inventors:
Daniel L. Chieng - Austin TX, US
Douglas D. Gephardt - Dripping Springs TX, US
Larry E. Hand - Meridian MS, US
Jeffrey M. Klaas - Lakeway TX, US
Adam Zaharias - Austin TX, US
Assignee:
D2Audio Corporation - Milpitas CA
International Classification:
G06F 17/00, G06F 9/30, G06F 9/40, H03G 3/00
US Classification:
700 94, 381104, 712208
Abstract:
Systems and methods for controlling the audio volume of an audio signal in an HDA codec having a programmable processor such as a DSP, wherein the codec receives digital audio signals and audio volume control verbs over an HDA bus, and the audio volume levels associated with the audio volume control verbs are used by the processor in the generation pulse width modulated (PWM) output signals, thereby controlling the audio volume levels of the output signals. The processor may be configured to adjust non-volume parameters such as PWM deadtime, in addition to adjusting audio volume, based on the audio volume levels. The codec may be implemented in a PC or other system that implements an HDA system that includes the HDA bus and HDA codec.


Jeffrey Klaas Photo 2

Systems And Methods For Communication Between A Pc Application And The Dsp In A Hda Audio Codec

US Patent:
2009006, Mar 5, 2009
Filed:
Sep 1, 2008
Appl. No.:
12/202356
Inventors:
Daniel L. Chieng - Austin TX, US
Douglas D. Gephardt - Dripping Springs TX, US
Larry E. Hand - Meridian MS, US
Jeffrey M. Klaas - Lakeway TX, US
Adam Zaharias - Austin TX, US
International Classification:
G06F 9/315
US Classification:
712225, 712E09034
Abstract:
Systems and methods implemented in a PC for enabling communication between an application executing on the CPU and a DSP that is incorporated into a codec in the High Definition Audio (HDA) system, wherein the communication is carried out via the HDA bus. In one embodiment, an HDA codec includes one or more conventional HDA widgets coupled to a programmable processor such as a DSP. The codec includes a set of registers that are configured to store HDA verbs and data transmitted via the HDA bus. The programmable processor is configured to identify verbs that indicate associated information is a communication from an application executing on the CPU, read the associated information, and process the information according to the associated verbs. The information may be program instructions, parametric data, requests for information, etc.


Jeffrey Klaas Photo 3

Systems And Methods For Shadowing An Hda Codec

US Patent:
8249730, Aug 21, 2012
Filed:
Sep 1, 2008
Appl. No.:
12/202360
Inventors:
Daniel L. Chieng - Austin TX, US
Douglas D. Gephardt - Dripping Springs TX, US
Jeffrey M. Klaas - Lakeway TX, US
Adam Zaharias - Austin TX, US
Assignee:
D2Audio Corporation - Milpitas CA
International Classification:
G06F 17/00
US Classification:
700 94
Abstract:
Systems and methods for “shadowing” a target codec to provide additional features that are not available in the target codec. In one embodiment, an audio amplification system includes a High Definition Audio (HDA) bus, and an HDA controller, a conventional HDA codec and a shadow HDA codec coupled to the HDA bus. The conventional codec receives audio data and commands from the HDA controller via the bus and processes them to generate an output audio signal. The shadow codec snoops the audio data and commands on the HDA bus that are targeted to the conventional codec. The shadow codec processes the snooped audio data and commands to generate a second audio output. The shadow codec does not communicate with the HDA controller and is transparent to the controller. The shadow codec does not request enumeration from the HDA controller and does not receive an address from the HDA controller.


Jeffrey Klaas Photo 4

Systems And Methods For Booting A Codec Processor Over A High Definition Audio Bus

US Patent:
8082438, Dec 20, 2011
Filed:
Sep 1, 2008
Appl. No.:
12/202359
Inventors:
Daniel L. Chieng - Austin TX, US
Douglas D. Gephardt - Dripping Springs TX, US
Jeffrey M. Klaas - Lakeway TX, US
Adam Zaharias - Austin TX, US
Assignee:
D2Audio Corporation - Milpitas CA
International Classification:
G06F 9/00, G06F 1/04, G06F 3/00, G06F 13/00, G06F 15/00, G10L 19/00, G10L 21/04, H05K 7/10
US Classification:
713 2, 713 1, 713375, 704500, 704503, 710 52, 710104, 710301, 712 32, 712220
Abstract:
Systems and methods for booting a programmable processor such as a DSP that is incorporated into an HDA codec. The codec and a system memory containing boot program instructions are connected to an HDA bus. In a first mode, the DSP receives boot program instructions via the HDA bus and boots using these instructions. In a second mode, the DSP boots from instructions that are contained in a memory that is connected to the DSP. In one embodiment, the memory connected to the DSP is a component of a plug-in card, and the DSP is configured to determine whether the plug-in card is present, then boot from the memory on the plug-in card if it is present or boot from the system memory via the HDA bus if the plug-in card is not present.


Jeffrey Klaas Photo 5

Systems And Methods For Overriding Hardwired Responses In An Hda Codec

US Patent:
8219226, Jul 10, 2012
Filed:
Sep 1, 2008
Appl. No.:
12/202358
Inventors:
Daniel L. Chieng - Austin TX, US
Douglas D. Gephardt - Dripping Springs TX, US
Jeffrey M. Klaas - Lakeway TX, US
Assignee:
D2Audio Corporation - Milpitas CA
International Classification:
G06F 17/00, G06F 13/00, G06F 9/30, G06F 9/40
US Classification:
700 94, 710 65, 712209, 712213
Abstract:
Systems and methods for overriding hardwired responses of a codec to High Definition Audio (HDA) verbs that are received from an HDA controller. In one embodiment, an HDA codec is configured to store one or more overriding responses, each of which is associated with a corresponding HDA verb. When an HDA verb is received by the codec, the codec determines whether the verb is associated with one of the overriding responses. If the verb is associated with one of the overriding responses, the overriding response is returned to the HDA controller. If the first HDA verb is not associated with one of the stored overriding responses, provide a hardwired response associated with the first HDA verb to the HDA bus. Overriding responses can be returned for unsupported verbs only, or for any verbs that prompt responses.


Jeffrey Klaas Photo 6

Variable Decimation Architecture For A Delta-Sigma Analog-To-Digital Converter

US Patent:
5157395, Oct 20, 1992
Filed:
Mar 4, 1991
Appl. No.:
7/664034
Inventors:
Bruce Del Signore - Austin TX
Eric J. Swanson - Austin TX
Jeffrey M. Klaas - Austin TX
David L. Medlock - Austin TX
Assignee:
Crystal Semiconductor Corporation - Austin TX
International Classification:
H03M 732, G06F 1531
US Classification:
341143
Abstract:
An analog-to-digital converter includes a delta-sigma modulator (10), having the output thereof filtered by a digital filter section. The digital filter section includes a first fixed decimation filter (12) followed by a variable decimation filter section (14) and an output low-pass filter section (16), having a fixed decimation ratio. The fixed variable decimation filter section (14) includes a single FIR filter (24) that has data processed therethrough with different sampling rates. A recursive controller (26) receives an external configuration input to determine the number of passes through the filter (24) that are required to provide the desired decimation ratio.