JEFFREY D BRADY, M.D.
Urology at Mills Ave, Orlando, FL

2009030, Dec 17, 2009

Jun 1, 2009

12/476202

Anthony P. DeLaurier - Los Altos CA, US
Mark Leather - Los Gatos CA, US
Robert S. Hartog - Windermere FL, US
Michael J. Mantor - Orlando FL, US
Mark C. Fowler - Hopkinton MA, US
Jeffrey T. Brady - Orlando FL, US
Marcos P. Zini - Oviedo FL, US

Advanced Micro Devices, Inc. - Sunnyvale CA

G09G 5/02, G06T 1/20

345589, 345506

Apparatus and systems utilizing multiple shader engines where each shader engine comprises multiple rows of shader engine filters combined with level one and level two cache systems. Each unified shader engine filter comprises a shader pipe array, and a texture mapping unit with access to a level one cache system and a level two cache. The shader pipe array accepts texture requests for a specified pixel from a resource and performs associated rendering calculations, outputting texel data. The texture mapping unit retrieves texel data stored in a level one cache system, with the ability to read and write to and from a level two cache system, and through formatting and bilinear filtering interpolations generates a formatted bilinear result based on the specific pixel's neighboring texels. Utilizing multiple rows of shader engine filters within a shader engine allows for the parallel processing of multiple simultaneous resource requests. Utilizing multiple shader engines allows for greater processing through the use of multiple simultaneous processing. A method utilizing multiple shader engines to perform texture mapping is also presented.

2009031, Dec 24, 2009

Jun 1, 2009

12/476152

Anthony P. DeLaurier - Los Altos CA, US
Mark Leather - Los Gatos CA, US
Robert S. Hartog - Windermere FL, US
Michael J. Mantor - Orlando FL, US
Jeffrey T. Brady - Orlando FL, US
Mark C. Fowler - Hopkinton MA, US
Marcos P. Zini - Oviedo FL, US

Advanced Micro Devices, Inc. - Sunnyvale CA

G06T 1/20, G09G 5/10

345589, 345506

Each row of a row based shader engine comprises a shader pipe array, a texture filter, and a level one texture cache system. The shader pipe array accepts texture requests for a specified pixel from a resource and performs associated rendering calculations, outputting texel data. The texture mapping unit receives texel data from a level one cache system and through formatting and bilinear filtering interpolations, generates a formatted bilinear result based on a specific pixel's corresponding four texels. Utilizing multiple rows of a row based shader engine within the shader engine allows for the parallel processing of multiple simultaneous resource requests. A method for texture filtering utilizing a row based shader engine is also presented.

2011005, Mar 3, 2011

Jan 21, 2010

12/691541

Michael MANTOR - Orlando FL, US
Ralph C. Taylor - Deland FL, US
Jeffrey T. Brady - Orlando FL, US

Advanced Micro Devices, Inc. - Sunnyvale CA

G09G 5/00

345581

A processor includes a first shader engine and a second shader engine. The first shader engine is configured to process pixel shaders for a first subset of pixels to be displayed on a display device. The second shader engine is configured to process pixel shaders for a second subset of pixels to be displayed on the display device. Both the first and second shader engines are also configured to process general-compute shaders and non-pixel graphics shaders. The processor may also include a level-one (L1) data cache, coupled to and positioned between the first and second shader engines.

7594069, Sep 22, 2009

Feb 26, 2004

10/788225

Jeffrey T. Brady - Orlando FL, US
Brian A. Buchner - Oviedo FL, US
Rex E. McCrary - Oviedo FL, US
Ralph C. Taylor - Deland FL, US

ATI Technologies, Inc. - Markham, Ontario

G06F 12/00

711112

An apparatus and method for single instruction multiple data caching includes a memory access request generator operative to receive a primary access request. The method and apparatus further includes a cache controller coupled to the memory access request generator, wherein the cache controller is operative to execute a memory request. The method and apparatus further includes a memory interface coupled to the cache controller, the memory interface operative to retrieve a plurality of requested data. The method and apparatus further includes a request processor coupled to the cache controller, the memory interface and the memory access request generator. The request processor is operative to receive a plurality of requested data and thereupon generate a plurality of parallel data outputs therefrom.

2012005, Mar 8, 2012

Sep 3, 2010

12/875757

James Conyngham - Austin TX, US
Jeffrey T. Brady - Orlando FL, US
Christopher L. Spencer - Oviedo FL, US

ADVANCED MICRO DEVICES, INC. - Sunnyvale CA

G06F 7/44, G06F 7/42

708503, 708504, 708505

A method and apparatus provides for performing floating-point division using input check/output correction floating-point division logic and a floating-point division fix-up instruction (e.g., an instruction, command, signal or other indicator). In one example, the apparatus includes a processor having a floating-point arithmetic logic unit (ALU) that includes the input check/output correction floating-point division logic. The input check/output correction floating-point division logic is responsive to the floating-point division fix-up instruction executable by the floating-point ALU that causes the input check/output correction floating-point division logic to examine a first input representing a numerator and a second input representing a denominator to determine whether a special case of floating-point division occurs. The floating-point division fix-up instruction also causes the input check/output correction floating-point division logic to provide an output representing a floating-point division result based on the determined special case of floating-point division and a third input representing a candidate quotient.

8468191, Jun 18, 2013

Jun 10, 2010

12/813074

Michael J. Mantor - Orlando FL, US
Jeffrey T. Brady - Orlando FL, US
Daniel B. Clifton - Chuluota FL, US
Christopher Spencer - Oviedo FL, US

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 7/48

708513

Systems and methods for multi-precision computation are disclosed. One embodiment of the present invention includes a plurality of multiply-add units (MADDs) configured to perform one or more single precision operations and an arrangement generator to generate one or more mantissa arrangements using a plurality of double precision numbers. Each MADD is configured to receive and load said mantissa arrangements from the arrangement generator. The MADDs compute a result of a multi-precision computation using the mantissa arrangements. In an embodiment, the MADDs are configured to simultaneously perform operations that include, single precision operations, double-precision additions and double-precision multiply and additions.

8473721, Jun 25, 2013

Apr 16, 2010

12/762020

Michael J. Mantor - Orlando FL, US
Jeffrey T. Brady - Orlando FL, US
Christopher L. Spencer - Oviedo FL, US
Daniel W. Wong - Cupertino CA, US
Andrew E. Gruber - Arlington MA, US

Advanced Micro Devices, Inc. - Sunnyvale CA
ATI Technologies ULC - Markham, Ontario

G06F 9/30

712221, 712300

Disclosed herein is a processing unit configured to process video data, and applications thereof. In an embodiment, the processing unit includes a buffer and an execution unit. The buffer is configured to store a data word, wherein the data word comprises a plurality of bytes of video data. The execution unit is configured to execute a single instruction to (i) shift bytes of video data contained in the data word to align a desired byte of video data and (ii) process the desired byte of the video data to provide processed video data.