JEFFREY COLIN BENZING
Pilots at Michaels Dr, Saratoga, CA

5620525, Apr 15, 1997

Aug 23, 1994

8/294513

Everhardus P. van de Ven - Saratoga CA
Eliot K. Broadbent - San Jose CA
Jeffrey C. Benzing - Saratoga CA
Barry L. Chin - Saratoga CA
Christopher W. Burkhart - Los Gatos CA

Novellus Systems, Inc. - San Jose CA

C23C 1600

118728

A platen supports a substrate on an interior platen region during the deposition of materials such as tungsten, metal nitrides, other metals, and silicides in a chemical vapor deposition ("CCVD") reactor. A deposition control gas composed of a suitable inert gas such as argon or a mixture of inert and reactive gases such as argon and hydrogen is introduced into the CVD reactor. Deposition control gas is preferably introduced through a restrictive opening in a gas orifice surrounding the platen interior region and exits near an edge of the substrate. The restrictive opening accommodates a uniform deposition control gas flow proximate to an edge of the substrate at a pressure greater than reactor pressure near the substrate edge. The deposition control gas substantially prevents process gas access to the substrate edge and backside. In one embodiment, the restrictive opening is formed by placing a restrictive insert within a gas groove surrounding the platen interior region.

5901271, May 4, 1999

Feb 26, 1997

8/806492

Jeffrey C. Benzing - Saratoga CA
Edward J. McInerney - San Jose CA
Michael N. Susoeff - San Jose CA

Novellus Systems, Inc. - San Jose CA

A01G 1306

392387

A cyclone evaporator includes an evaporator body with an evaporation chamber therein. The evaporation chamber preferably includes a thermally conductive sidewall having a generally cylindrical upper portion and a downwardly tapered lower portion. The evaporator body further includes a cover having a vapor outlet opening into the evaporation chamber and an outlet tube. The outlet tube circumscribes the vapor outlet and extends into a lower portion of the evaporation chamber. A liquid precursor passage and a carrier gas passage extend through the evaporator body and open into the evaporation chamber. In one embodiment, the carrier gas passage is positioned to direct carrier gas parallel to liquid precursor flow and intersect the liquid precursor at a liquid precursor passage outlet within the evaporation chamber. In another embodiment, the carrier gas passage is positioned to direct carrier gas across an outlet of liquid precursor passage. In both embodiments, the carrier gas facilitates atomization of the liquid precursor and flows cyclonically to distribute the atomized liquid precursor within the evaporation chamber.

5882417, Mar 16, 1999

Dec 31, 1996

8/775857

Everhardus P. van de Ven - Cupertino CA
Eliot K. Broadbent - Beaverton OR
Jeffrey C. Benzing - Saratoga CA
Barry L. Chin - Sunnyvale CA
Christopher W. Burkhart - Los Gatos CA
Lawrence C. Lane - San Jose CA
Edward John McInerney - San Jose CA

Novellus Systems, Inc. - San Jose CA

C23C 1600

118728

A platen supports a wafer during the deposition of tungsten, metal nitrides, other metals, and silicides in a chemicalvapor deposition reactor. A deposition control gas that includes a suitable inert gas such as argon or a mixture of inert and reactant gases such as argon and hydrogen is introduced through a restrictive opening into an ambient in the reactor. An exclusion guard aligned with the platen has an extension extending over a frontside peripheral region of the wafer. Deposition control gas is introduced under the exclusion guard extension and exits through a restrictive opening between the exclusion guard extension and a wafer frontside peripheral region. The restrictive opening provides a uniform pressure of deposition control gas at the edge and frontside of the wafer to prevent deposition on the wafer edge and backside.

6126382, Oct 3, 2000

Nov 26, 1997

8/980125

Martin N. Scales - San Jose CA
David A. Pechin - Santa Clara CA
Jeffrey C. Benzing - Saratoga CA
R. Marshall Stowell - Lakeworth FL

Novellus Systems, Inc. - San Jose CA

G01N 2130

414754

A passive mechanism for centering a wafer on a chuck and with respect to a backside exclusion gas ring includes a plurality of wheels that are rotatably mounted in a circular pattern at the top surface of a chuck. The axis of rotation of each wheel is parallel to the top surface of the chuck and perpendicular to a radius extending outward from the centerpoint of the chuck surface. When a wafer is placed on the chuck, its edge contacts the wheels and, by its own weight, the wafer moves toward the center of the chuck, thereby centering itself. The wafer either slides on the wheels or, if the frictional force between the wafer and one or more of the wheels is great enough, the wafer causes the wheel to turn. The wheels may be mounted on the chuck, a carrier ring or a wafer transfer arm for moving wafers between processing stations. In one embodiment the alignment wheels are mounted on a carrier ring, and a second alignment mechanism aligns the carrier ring to the chuck.

7501339, Mar 10, 2009

Mar 23, 2006

11/389428

Jay E. Uglow - Livermore CA, US
Nicolas J. Bright - San Jose CA, US
Dave J. Hemker - San Jose CA, US
Kenneth P. MacWilliams - Monte Sereno CA, US
Jeffrey C. Benzing - Saratoga CA, US
Timothy M. Archer - Portland OR, US

Lam Research Corporation - Fremont CA

H01L 21/4763

438623

A dielectric structure and method for making a dielectric structure for dual-damascene applications over a substrate are provided. The method includes forming a barrier layer over the substrate, forming an inorganic dielectric layer over the barrier layer, and forming a low dielectric constant layer over the inorganic dielectric layer. In this preferred example, the method also includes forming a trench in the low dielectric constant layer using a first etch chemistry. The etching is timed to etch through a partial thickness of the low dielectric constant layer and the first etch chemistry is optimized to a selected low dielectric constant material. The method further includes forming a via hole in the inorganic dielectric layer using a second etch chemistry, such that the via is within the trench. In a specific example, the inorganic dielectric layer can be an un-doped TEOS oxide or a fluorine doped oxide, and the low dielectric constant layer can be a carbon doped oxide (C-oxide) or other low K dielectrics.

6909190, Jun 21, 2005

Feb 16, 2001

09/788105

Jay E. Uglow - Livermore CA, US
Nicolas J. Bright - San Jose CA, US
Dave J. Hemker - San Jose CA, US
Kenneth P. MacWilliams - Monte Sereno CA, US
Jeffrey C. Benzing - Saratoga CA, US
Timothy M. Archer - Portland OR, US

Lam Research Corporation - Fremont CA

H01L023/48

257759, 257758, 257774

A dielectric structure and method for making a dielectric structure for dual-damascene applications over a substrate are provided. The method includes forming a barrier layer over the substrate, forming an inorganic dielectric layer over the barrier layer, and forming a low dielectric constant layer over the inorganic dielectric layer. In this preferred example, the method also includes forming a trench in the low dielectric constant layer using a first etch chemistry, and forming a via in the inorganic dielectric layer using a second etch chemistry, such that the via is within the trench. In another specific example, the inorganic dielectric layer can be an un-doped TEOS oxide or a fluorine doped oxide, and the low dielectric constant layer can be a carbon doped oxide (C-oxide) or other low K dielectrics.

7060605, Jun 13, 2006

Feb 16, 2001

09/785999

Jay E. Uglow - Livermore CA, US
Nicolas J. Bright - San Jose CA, US
Dave J. Hemker - San Jose CA, US
Kenneth P. MacWilliams - Monte Sereno CA, US
Jeffrey C. Benzing - Saratoga CA, US
Timothy M. Archer - Portland OR, US

Lam Research Corporation - Fremont CA

H01L 21/4763

438624

A dielectric structure and method for making a dielectric structure for dual-damascene applications over a substrate are provided. The method includes forming a barrier layer over the substrate, forming an inorganic dielectric layer over the barrier layer, and forming a low dielectric constant layer over the inorganic dielectric layer. In this preferred example, the method also includes forming a trench in the low dielectric constant layer using a first etch chemistry, and forming a via in the inorganic dielectric layer using a second etch chemistry, such that the via is within the trench. In another specific example, the inorganic dielectric layer can be an un-doped TEOS oxide or a fluorine doped oxide, and the low dielectric constant layer can be a carbon doped oxide (C-oxide) or other low K dielectrics.

5405480, Apr 11, 1995

Jul 11, 1994

8/273574

Jeffrey C. Benzing - Saratoga CA
Eliot K. Broadbent - San Jose CA
J. Kirkwood H. Rough - San Jose CA

Novellus Systems, Inc. - CA

H01L 2100

156345

An induction plasma source for integrated circuit fabrication includes a hemispherically shaped induction coil in an expanding spiral pattern about the vacuum chamber containing a semiconductor wafer supported by a platen. The windings of the induction coil follow the contour of a hemispherically shaped quartz bell jar, which holds the vacuum. The power source is a low frequency rf source having a frequency of about 450 KHz and a power in the range of 200-2000 watts, and the pressure is a low pressure of about 0. 1-100 mTorr. A high frequency rf source independently adjusts the bias voltage on the wafer.

5605599, Feb 25, 1997

Feb 17, 1995

8/390337

Jeffrey C. Benzing - Saratoga CA
Eliot K. Broadbent - San Jose CA
J. Kirkwood H. Rough - San Jose CA

Novellus Systems, Inc. - San Jose CA

B44C 122

1566431

An induction plasma source for integrated circuit fabrication includes a hemispherically shaped induction coil in an expanding spiral pattern about the vacuum chamber containing a semiconductor wafer supported by a platen. The windings of the induction coil follow the contour of a hemispherically shaped quartz bell jar, which holds the vacuum. The power source is a low frequency rf source having a frequency of about 450 KHz and a power in the range of 200-2000 Watts, and the pressure is a low pressure of about 0. 1-100 mTorr. A high frequency rf source independently adjusts the bias voltage on the wafer.

6225744, May 1, 2001

Feb 24, 1997

8/804584

Jeffrey A. Tobin - Mountain View CA
Jeffrey C. Benzing - Saratoga CA
Eliot K. Broadbent - Beaverton OR
J. Kirkwood H. Rough - San Jose CA

Novellus Systems, Inc. - San Jose CA

H01J 724

31511151

An induction plasma source for integrated circuit fabrication includes an induction coil which defines a generally convex surface. The convex surface may be in the form of a spherical section less than a hemisphere, a paraboloid, or some other smooth convex surface. The windings of the induction coil may be spaced at different intervals in different sections of the coil and may be in multiple layers in at least a portion of the coil. Varying the shape of the coil and the distribution of the coil windings allows the plasma to be shaped in a desired manner.