JEFF FORREST SMITH
Pilots at Colwick Ct, Plano, TX
License number
Texas A1772549
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
3913 Colwick Ct, Plano, TX 75023
Organization information
See more information about JEFF FORREST SMITH at bizstanding.comJeff Forrest Smith Attorney
1400 Preston Rd, Plano, TX 75093
Industry:
Legal Services Office
Phone:
(972) 665-9948 (Phone)
Categories:
Attorneys
Jeff Forrest Smith PC
Dallas, TX - Plano, TX
Status:
Inactive
Doing business as:
Jeff Forrest Smith, PC
Registration:
Feb 10, 2000
Addresses:
6750 Hillcrest Plz Dr #214, Dallas, TX 75230
3913 Colwick Ct, Plano, TX 75023
3913 Colwick Ct, Plano, TX 75023
State ID:
0092636102
Business type:
Domestic Professional Corporation
President, Director:
Jeff Forrest Smith President, Director, inactive
TIN:
17528615259
Professional information
Jeff Smith - Plano, TX
Work:
Design by Jeff Smith
Freelance Web and Marketing Design by Jeff Smith
Web Developer Virtual Book Worm
Editor/ Graphic Designer The Mobile Solution
Assistant Manager
Freelance Web and Marketing Design by Jeff Smith
Web Developer Virtual Book Worm
Editor/ Graphic Designer The Mobile Solution
Assistant Manager
Education:
Texas A&M University - College Station, TX
Bachelor of Science in Industrial Distribution
Bachelor of Science in Industrial Distribution
Transistors Formed With Grid Or Island Implantation Masks To Form Reduced Diffusion-Depth Regions Without Additional Masks And Process Steps
US Patent:
6716709, Apr 6, 2004
Filed:
Dec 31, 2002
Appl. No.:
10/335322
Inventors:
Lily Springer - Dallas TX
Jeff Smith - Plano TX
Sheldon Haynie - Amherst NH
Joe R. Trogolo - Plano TX
Jeff Smith - Plano TX
Sheldon Haynie - Amherst NH
Joe R. Trogolo - Plano TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 21336
US Classification:
438301, 438270, 438279
Abstract:
A method of forming two regions having differing depths using a single implantation process is provided. A mask having two openings associated therewith is formed over a semiconductor body, wherein one of the openings has a size larger than an implantation design rule, and the other opening has a size smaller than the design rule. An implant is performed into the semiconductor body through the implant mask, resulting in two distinct doped regions, wherein the region associated with the larger opening has more dopant than the region associated with the smaller opening. Subsequent activation and thermal processing results in the one region diffusing a greater amount than the second region, thereby resulting in two regions formed concurrently having different depths.
Transistors Formed With Grid Or Island Implantation Masks To Form Reduced Diffusion-Depth Regions Without Additional Masks And Process Steps
US Patent:
6869851, Mar 22, 2005
Filed:
Jan 20, 2004
Appl. No.:
10/761438
Inventors:
Joe R. Trogolo - Plano TX, US
Lily Springer - Dallas TX, US
Jeff Smith - Plano TX, US
Sheldon Haynie - Amherst NH, US
Lily Springer - Dallas TX, US
Jeff Smith - Plano TX, US
Sheldon Haynie - Amherst NH, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L021/336, H01L021/8836
US Classification:
438301, 438279, 438270
Abstract:
A method of forming two regions having differing depths using a single implantation process is provided. A mask having two openings associated therewith is formed over a semiconductor body, wherein one of the openings has a size larger than an implantation design rule, and the other opening has a size smaller than the design rule. An implant is performed into the semiconductor body through the implant mask, resulting in two distinct doped regions, wherein the region associated with the larger opening has more dopant than the region associated with the smaller opening. Subsequent activation and thermal processing results in the one region diffusing a greater amount than the second region, thereby resulting in two regions formed concurrently having different depths.
Jeff Smith - Plano, TX
Work:
Blockbuster, Inc
Corporate Category Manager-Electronics CompUSA, Inc
Senior Category Manager-Numerous Categories Highland Superstores, Inc
Divisional Merchandise Manager-Numerous Categories
Corporate Category Manager-Electronics CompUSA, Inc
Senior Category Manager-Numerous Categories Highland Superstores, Inc
Divisional Merchandise Manager-Numerous Categories
Education:
Wayne State University
Pre-Medicine/Liberal Arts
Pre-Medicine/Liberal Arts
Skills:
Cultivating Business Relationships Suppliers/Vendors Negotiations Organizational Leadership
Versatile System For Optimizing Current Gain In Bipolar Transistor Structures
US Patent:
2007020, Sep 6, 2007
Filed:
May 8, 2007
Appl. No.:
11/745906
Inventors:
Joe Trogolo - Plano TX, US
Tathagata Chatterlee - Allen TX, US
Lily Springer - Dallas TX, US
Jeff Smith - Plano TX, US
Tathagata Chatterlee - Allen TX, US
Lily Springer - Dallas TX, US
Jeff Smith - Plano TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 29/739
US Classification:
257198000, 257E29005, 257E29174
Abstract:
Disclosed are apparatus and methods for designing electrical contact for a bipolar emitter structure. The area of an emitter structure () and the required current density throughput of an electrical contact structure () are determined. A required electrical contact area is determined based on the required current density, and the electrical contact structure is then designed to minimize the required electrical contact area with respect to the emitter structure area.
Versatile System For Optimizing Current Gain In Bipolar Transistor Structures
US Patent:
7226835, Jun 5, 2007
Filed:
Jul 15, 2002
Appl. No.:
10/196634
Inventors:
Joe Trogolo - Plano TX, US
Tathagata Chatterlee - Richardson TX, US
Lily Springer - Dallas TX, US
Jeff Smith - Plano TX, US
Tathagata Chatterlee - Richardson TX, US
Lily Springer - Dallas TX, US
Jeff Smith - Plano TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 31/0328
US Classification:
438235, 257197, 257198, 257565
Abstract:
Disclosed are apparatus and methods for designing electrical contact for a bipolar emitter structure. The area of an emitter structure () and the required current density throughput of an electrical contact structure () are determined. A required electrical contact area is determined based on the required current density, and the electrical contact structure is then designed to minimize the required electrical contact area with respect to the emitter structure area.