JAVIER FRANCIS IZQUIERDO
Pilots at Sunlight Oak Ln, Houston, TX
License number
Texas A2796496
Issued Date
Mar 2016
Expiration Date
Mar 2018
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
9126 Sunlight Oak Ln, Houston, TX 77070
Professional information
Director, Power Systems Development At Hp
Position:
Director, Power Systems Development at HP
Location:
Houston, Texas Area
Industry:
Computer Hardware
Work:
HP
since Jun 2007
-
Director, Power Systems Development
Compaq
Jun 1996 - May 2007
-
Director, Storage Development
Compaq
- Houston Mar 1990 - May 1996
-
Program Manager, Server Platform Development
Compaq
- Houston Mar 1988 - May 1990
-
Engineer
Texas Instruments
1981 - 1988
-
engineer
Education:
Texas A&M University 1977 - 1981
BSEE
BSEE
Multiprocessor System Including Interprocessor Encoding And Decoding Logic For Communication Between Two Cards Through Reduced Addressing Lines
US Patent:
5884054, Mar 16, 1999
Filed:
Jan 6, 1993
Appl. No.:
8/001091
Inventors:
Javier F. Izquierdo - Houston TX
John A. Landry - Tomball TX
John A. Landry - Tomball TX
Assignee:
Compaq Computer Corporation - Houston TX
International Classification:
G06F 1300
US Classification:
395307
Abstract:
A method for communication between multiple processors using registers that are accessed by four register select lines which are translated from the original system address. The address translation is performed off of the main processor board to reduce loading effects on the local bus and reduces the pin count of processor board. A signal representing which of the processors is currently active is used as a pseudo address line for the purpose of the translation. The original addresses of the I/O registers may be either input/output or memory mapped.
Multiprocessing System Includes Interprocessor Encoding And Decoding Logic Used For Communication Between Two Cards Through Reduced Addressing Lines
US Patent:
5201055, Apr 6, 1993
Filed:
Nov 3, 1989
Appl. No.:
7/431659
Inventors:
Javier F. Izquierdo - Houston TX
John A. Landry - Tomball TX
John A. Landry - Tomball TX
Assignee:
Compaq Computer Corporation - Houston TX
International Classification:
G06F 1300, G06F 1516
US Classification:
395800
Abstract:
A method for communication between multiple processors using registers that are accessed by four register select lines which are translated from the original system address. The address translation is performed off of the main processor board to reduce loading effects on the local bus and reduces the pin count of processor board. A signal representing which of the processors is currently active is used as a pseudo address line for the purpose of the translation. The original addresses of the I/O registers may be either input/output or memory mapped.
Daisy-Chained Serial Shift Register For Determining Configuration Of Removable Circuit Boards In A Computer System
US Patent:
5287531, Feb 15, 1994
Filed:
Oct 31, 1990
Appl. No.:
7/606165
Inventors:
Harry R. Rogers - Spring TX
John A. Landry - Tomball TX
Javier F. Izquierdo - Houston TX
John A. Landry - Tomball TX
Javier F. Izquierdo - Houston TX
Assignee:
Compaq Computer Corp. - Houston TX
International Classification:
G06F 1202
US Classification:
395800
Abstract:
An apparatus for determining system configuration in a computer system using only one 8 bit data port. Permanent connections on each of the microprocessor and memory boards provide respective configuration and/or memory information about each board. The signals are stored in serial out shift registers associated with each board that are daisy chained together. These shift registers serially transmit the configuration information to one 8 bit data port, which then transmits this information to the computer system in 8 bit increments. If a given slot is empty it is automatically bypassed in the shift register daisy chain.
Power Distribution To Computer System
US Patent:
2012008, Apr 5, 2012
Filed:
Jun 23, 2009
Appl. No.:
13/320947
Inventors:
Javier F. Izquierdo - Houston TX, US
Ronald D. Noblett - Bellaire TX, US
Ronald D. Noblett - Bellaire TX, US
International Classification:
G06F 1/26
US Classification:
713300
Abstract:
Power distribution to computer systems. At least some of the illustrative embodiments are systems including a power supply configured to convert an alternating current (AC) power signal to a direct current (DC) power signal (and the power supply comprising a first power port and a second power port, the second power port different than the first power port), a first computer system coupled to the first power port (the power supply configured to provide DC operational power to the first computer system through the first power port, and the first computer system the only computer system receiving operational power through the first power port), and a second computer system different than the first computer system (the second computer system coupled to the second power port, the power supply configured to provide DC operational power to the second computer system through the second power port, and the second computer system the only computer system receiving operational power from the second power port).
Method And Apparatus For Independently Resetting Processors And Cache Controllers In Multiple Processor Systems
US Patent:
5611078, Mar 11, 1997
Filed:
Jun 7, 1995
Appl. No.:
8/480874
Inventors:
David A. Miller - Houston TX
Kenneth A. Jansen - Spring TX
Paul R. Culley - Cypress TX
Mark Taylor - Houston TX
Javier F. Izquierdo - Houston TX
Kenneth A. Jansen - Spring TX
Paul R. Culley - Cypress TX
Mark Taylor - Houston TX
Javier F. Izquierdo - Houston TX
Assignee:
Compaq Computer Corporation - Houston TX
International Classification:
G06F 1300
US Classification:
395653
Abstract:
A method and system for independently resetting primary and secondary processors 20 and 120 respectively under program control in a multiprocessor, cache memory system. Processors 20 and 120 are reset without causing cache memory controllers 24 and 124 to reset.
Multiprocessor Communication Using Reduced Addressing Lines
US Patent:
6154804, Nov 28, 2000
Filed:
Feb 15, 1999
Appl. No.:
9/250232
Inventors:
Javier F. Izquierdo - Houston TX
John A. Landry - Tomball TX
John A. Landry - Tomball TX
Assignee:
Compaq Computer Corporation - Houston TX
International Classification:
G06F 1300
US Classification:
710130
Abstract:
A method for communication between multiple processors using registers that are accessed by four register select lines which are translated from the original system address. The address translation is performed off of the main processor board to reduce loading effects on the local bus and reduces the pin count of processor board. A signal representing which of the processors is currently active is used as a pseudo address line for the purpose of the translation. The original addresses of the I/O registers may be either input/output or memory mapped.
Multi-Processor System With System Wide Reset And Partial System Reset Capabilities
US Patent:
5870602, Feb 9, 1999
Filed:
Jan 27, 1998
Appl. No.:
/014369
Inventors:
David A. Miller - Houston TX
Kenneth A. Jansen - Spring TX
Paul R. Culley - Cypress TX
Mark Taylor - Houston TX
Javier F. Izquierdo - Houston TX
Kenneth A. Jansen - Spring TX
Paul R. Culley - Cypress TX
Mark Taylor - Houston TX
Javier F. Izquierdo - Houston TX
Assignee:
Compaq Computer Corporation - Houston TX
International Classification:
G06F 900
US Classification:
395651
Abstract:
A multiprocessor system includes first and second processing units. Each of these processing units includes at least a processor and preferably also a cache memory, a cache memory controller and a numerical coprocessor. Each processing unit is reset in response to a system reset signal but only selected portions of the processing units are reset in response to a partial-reset signal. The system can also include a number other components such as video circuitry, a hard disk drive, bus interface circuitry, a speaker, a keyboard controller and a keyboard.
Method And Apparatus For Independently Resetting Processors And Cache Controllers In Multiple Processor Systems
US Patent:
5737604, Apr 7, 1998
Filed:
Sep 30, 1996
Appl. No.:
8/723841
Inventors:
David A. Miller - Houston TX
Kenneth A. Jansen - Spring TX
Paul R. Culley - Cypress TX
Mark Taylor - Houston TX
Javier F. Izquierdo - Houston TX
Kenneth A. Jansen - Spring TX
Paul R. Culley - Cypress TX
Mark Taylor - Houston TX
Javier F. Izquierdo - Houston TX
Assignee:
Compaq Computer Corporation - Houston TX
International Classification:
G06F 900
US Classification:
395651
Abstract:
A method and system for independently resetting primary and secondary processors 20 and 120 respectively under program control in a multiprocessor, cache memory system. Processors 20 and 120 are reset without causing cache memory controllers 24 and 124 to reset.
Sine Wave Clock Distribution With High Voltage Output
US Patent:
5281861, Jan 25, 1994
Filed:
Mar 19, 1992
Appl. No.:
7/855453
Inventors:
Thanh T. Tran - Tomball TX
Clarence Y. Mar - Austin TX
Javier F. Izquierdo - Houston TX
Clarence Y. Mar - Austin TX
Javier F. Izquierdo - Houston TX
Assignee:
Compaq Computer Corporation - Houston TX
International Classification:
H03K 500, H03K 513, H03K 700, H03B 1900
US Classification:
307269
Abstract:
A clock signal is distributed over a circuit board and across a connector as a sine wave. A circuit located near the clocked circuitry converts the sine wave into a same frequency square wave for use by the clocked circuitry. The output stage of the converter circuitry provides a high output level to drive CMOS circuitry. The output transistor is pulled up to 5 volts, but the preceding transistors are pulled up to 6. 3 volts so that the base to emitter drops are compensated.