Jason P Moore
Architects in Albuquerque, NM
License number
Colorado 300492
Issued Date
Jul 12, 1963
Renew Date
Jul 31, 1991
Expiration Date
Jul 31, 1991
Type
Architect
Address
Address
PO Box 8266, Albuquerque, NM 87108
Personal information
See more information about Jason P Moore at radaris.comName
Address
Phone
7600 Montgomery Blvd NE, Albuquerque, NM 87109
7225 Prairie Rd NE, Albuquerque, NM 87109
8911 Northeastern Blvd NE, Albuquerque, NM 87112
Professional information
See more information about Jason P Moore at trustoria.com
Engineering Director At Xilinx
Engineering Director At Xilinx
Position:
Engineering Director at Xilinx
Location:
Albuquerque, New Mexico Area
Industry:
Defense & Space
Work:
Xilinx
since Oct 2000
-
Engineering Director
Motorola Government Group
Jan 1993 - Oct 2000
-
Hardware Engineer / Systems Engineer
Education:
Arizona State University 1995 - 1998
New Mexico State University 1988 - 1992
BS, Electrical Engineering
New Mexico State University 1988 - 1992
BS, Electrical Engineering
Director, A&Amp;D Applications Engineering At Xilinx
Director, A&Amp;D Applications Engineering At Xilinx
Position:
Director, A&D Applications Engineering at Xilinx
Location:
United States
Work:
Xilinx
- Albuquerque, NM since Oct 2000
-
Director, A&D Applications Engineering
Motorola Government Group
- Scottsdale, Arizona Jan 1993 - Oct 2000
-
HW/ASIC Designer and Project Lead
Education:
New Mexico State University 1987 - 1992
Bachelor of Science (B.S.), Electrical and Electronics Engineering
Bachelor of Science (B.S.), Electrical and Electronics Engineering
Jason Moore, Albuquerque NM
Jason Moore, Albuquerque NM
Work:
ERA
Albuquerque
(505) 296-1500
Albuquerque
(505) 296-1500
Method And Integrated Circuit For Protecting Against Differential Power Analysis Attacks
Method And Integrated Circuit For Protecting Against Differential Power Analysis Attacks
US Patent:
8539254, Sep 17, 2013
Filed:
Jun 1, 2010
Appl. No.:
12/791608
Inventors:
Brendan K. Bridgford - New Haven CT, US
Jason J. Moore - Albuquerque NM, US
Stephen M. Trimberger - San Jose CA, US
Eric E. Edwards - Albuquerque NM, US
Jason J. Moore - Albuquerque NM, US
Stephen M. Trimberger - San Jose CA, US
Eric E. Edwards - Albuquerque NM, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H04L 29/06
US Classification:
713194, 713100, 713187, 713330, 726 17, 726 21
Abstract:
In one embodiment of the invention, a method is provided for protecting against attacks on security of a programmable integrated circuit (IC). At least a portion of an encrypted bitstream input to the programmable IC is decrypted with a cryptographic key stored in the programmable IC. A number of failures to decrypt the encrypted bitstream is tracked. The tracked number is stored in a memory of the programmable IC that retains the number across on-off power cycles of the programmable IC. In response to the number of failures exceeding a threshold, data that prevents the decryption key from being used for a subsequent decryption of a bitstream is stored in the programmable IC.
Circuit For And Method Of Implementing A Plurality Of Circuits On A Programmable Logic Device
Circuit For And Method Of Implementing A Plurality Of Circuits On A Programmable Logic Device
US Patent:
7408381, Aug 5, 2008
Filed:
Feb 14, 2006
Appl. No.:
11/353748
Inventors:
Saar Drimer - Cambridge, GB
Jason J. Moore - Albuquerque NM, US
Austin H. Lesea - Los Gatos CA, US
Jason J. Moore - Albuquerque NM, US
Austin H. Lesea - Los Gatos CA, US
Assignee:
XILINX, Inc. - San Jose CA
International Classification:
H03K 19/177, H01L 25/00, G06F 12/14
US Classification:
326 41, 326 38, 326 47, 713189
Abstract:
A circuit for implementing a plurality of circuits on a programmable logic device, the circuit comprising a first circuit implemented on a first portion of the programmable logic device; a second circuit implemented on a second portion of the programmable logic device; and a control circuit coupled to the first circuit and the second circuit, the control circuit providing isolation between the first circuit and the second circuit. While the first circuit and the second circuit may comprise redundant circuits implementing a common function, the circuits may also comprise circuits which must be isolated, such as an encryption circuit and a decryption circuit implementing a cryptographic function. A method for implementing a plurality of circuits on a programmable logic device is also disclosed.
Isolation Verification Within Integrated Circuits
Isolation Verification Within Integrated Circuits
US Patent:
7949974, May 24, 2011
Filed:
Feb 28, 2008
Appl. No.:
12/038837
Inventors:
Jason J. Moore - Albuquerque NM, US
Ian L. McEwen - Golden CO, US
Reto Stamm - Sunnyvale CA, US
John Damian Corbett - Santa Clara CA, US
Eric M. Shiflet - Boulder CO, US
Ian L. McEwen - Golden CO, US
Reto Stamm - Sunnyvale CA, US
John Damian Corbett - Santa Clara CA, US
Eric M. Shiflet - Boulder CO, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716111, 716116
Abstract:
A computer-implemented method of verifying isolation between a plurality of modules of a circuit design to be implemented within an integrated circuit can include identifying a first module and at least a second module of the circuit design for the integrated circuit. One or more circuit attributes indicative of isolation between the first module and the second module can be identified and compared with at least one isolation criterion. An indication of whether the first module is isolated from the second module can be output according to results of the comparison.
Verification Of Logic Core Implementation
Verification Of Logic Core Implementation
US Patent:
8286113, Oct 9, 2012
Filed:
Jan 11, 2011
Appl. No.:
13/004183
Inventors:
Brendan K. Bridgford - Vienna VA, US
Jason J. Moore - Albuquerque NM, US
Derrick S. Woods - Loveland CO, US
Jason J. Moore - Albuquerque NM, US
Derrick S. Woods - Loveland CO, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 17/50, G06F 15/177, G06F 9/00
US Classification:
716117, 716121, 716128, 716107, 716136, 713 2, 713100
Abstract:
A system and method are provided for verifying implementation of a logic core in a complete bitstream. A logic core bitstream is extracted from the complete bitstream. The logic core bitstream is compared to a reference bitstream of the logic core for a target device. In response to no discrepancy in the comparison of the logic core bitstream and the reference bitstream, a data value is stored indicating that the logic core implementation contained in the complete bitstream is verified.
Method And Integrated Circuit For Secure Encryption And Decryption
Method And Integrated Circuit For Secure Encryption And Decryption
US Patent:
8379850, Feb 19, 2013
Filed:
Oct 8, 2010
Appl. No.:
12/900805
Inventors:
Brendan K. Bridgford - Vienna VA, US
Stephen M. Trimberger - San Jose CA, US
Jason J. Moore - Albuquerque NM, US
Edward S. Peterson - Rio Rancho NM, US
James Wesselkamper - Albuquerque NM, US
John C. Hoffman - Corrales NM, US
Stephen M. Trimberger - San Jose CA, US
Jason J. Moore - Albuquerque NM, US
Edward S. Peterson - Rio Rancho NM, US
James Wesselkamper - Albuquerque NM, US
John C. Hoffman - Corrales NM, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H04L 9/00, H04K 1/04
US Classification:
380 45, 380 37, 713187, 713189
Abstract:
In one embodiment, a cryptographic device is provided. The cryptographic device includes a persistent memory and a decryption control circuit coupled to the persistent memory. The decryption control circuit is configured to receive an encrypted data stream and decrypt a first portion of the encrypted data stream using a first cryptographic key stored in the persistent memory, the first portion including a second cryptographic key. The decryption circuit is configured to decrypt a second portion of the encrypted data stream using the second cryptographic key, the second portion of the encrypted data stream including payload data.