Jason Andres Gonzalez
Dentist at Forecastle Dr, Fort Collins, CO

6756858, Jun 29, 2004

Dec 12, 2001

10/015350

Jason Gonzalez - Ft Collins CO
M. Jason Welch - Ft. Collins CO

Agilent Technologies, Inc. - Palo Alto CA

H03H 740

333 173, 327362, 326 30

A method for matching output impedance of a driver to a load impedance. In representative embodiments an external impedance is attached between an external contact and a first source potential, wherein the load impedance includes the external impedance plus impedance of interconnections between an output terminal of the driver and the external impedance. An adjustable impedance, which can be field effect transistors which can be turned on separately and in combination to change the value of the adjustable impedance and which can be located on an integrated circuit, are connected between a second source potential and the output terminal of the driver. A reference potential, wherein the reference potential has a value half-way between the first source potential and the second source potential is obtained. And a load matching impedance is obtained by changing the adjustable impedance until the absolute value of the difference between the voltage of the output terminal of the driver and the reference potential is less than a preselected value.

6834381, Dec 21, 2004

Jan 10, 2002

10/044122

Jason Gonzalez - Ft Collins CO

Agilent Technolgies, Inc. - Palo Alto CA

G06F 1750

716 13, 716 6

A novel method and apparatus is presented for controlling the slew rate of a transitioning signal on an integrated circuit transmission line. The signal driver which drives the signal onto the transmission line is connected to the transmission line via redistribution metal characterized by a characteristic capacitance appropriate to adjust the RC time constant of the transmission line to shape the signal edges to a slope resulting in the desired slew rate.

7210114, Apr 24, 2007

Oct 5, 2004

10/958316

Jason Gonzalez - Fort Collins CO, US

Avago Technologies General IP (Singapore) Pte. Ltd. - Singapore

G06F 17/50, G06F 9/45

716 13, 716 6

A novel method is presented for mapping a signal driver of an integrated circuit to one of a plurality of interconnect pads. The output impedance of the signal driver and desired slew rate for a signal generated by the signal driver is used to calculate a desired characteristic capacitance to provide a resulting characteristic time constant required to achieve the desired slew rate on a transmission line connected to receive the signal. The characteristic capacitance associated with each at least one possible interconnection path between the driver and pad is estimated, and one of the interconnection paths whose associated characteristic capacitance is substantially equal to the desired characteristic capacitance is selected, and the output driver is then mapped to the pad associated with the selected interconnection path.

6777755, Aug 17, 2004

Dec 5, 2001

10/008123

Guy Harlan Humphrey - Fort Collins CO
C. Stephen Dondale - Ft. Collins CO
Jason Gonzalez - Ft Collins CO

Agilent Technologies, Inc. - Palo Alto CA

H01L 2362

257360, 257363, 257357, 257358, 257533, 257537

An electrostatic discharge (ESD) structure for use in an integrated circuit (IC). The ESD structure comprises a metallic resistor and a metallic capacitor that are electrically coupled in series to form a resistor-capacitor (RC) component having an appropriate RC time constant. The RC component maintains a level of charge between ground and a shunt node to ensure that, during an ESD event, electrostatic charge on a power supply, VDD, associated with the ESD structure is shunted via a shunt path from said power supply VDD to said ground. By using metal to create the metal resistor and capacitor, charge leakage problems that result from parasitic capacitance associated with using an RC component comprised of either a poly, active, or nwell resistor in combination a diode are eliminated. By eliminating such charge leakage problems, a more reliable RC component, and thus a more reliable RC time constant, are obtained.

7123039, Oct 17, 2006

Aug 13, 2004

10/917766

Jason Gonzalez - Fort Collins CO, US

G01R 31/26, G01R 31/02, G01R 31/3187

324763, 324765, 324537

An integrated circuit (IC) measures a voltage at an interface of the IC. The IC comprises voltage reference, comparator, and control circuits. The voltage reference circuit provides reference voltages responsive to a control input. The comparator circuit compares a first reference voltage with a voltage at the interface. The control circuit receives an output of the comparator and adjusts the control input to provide a second reference voltage closer to the voltage at the interface. A method for measuring voltage at an IC interface comprises generating a first reference voltage, monitoring the voltage at the interface from within the IC, comparing the first reference and interface voltages, generating a second reference voltage responsive to a result of the comparing, replacing the first reference voltage with the second reference voltage, and repeating until an applied reference voltage is substantially equal to the voltage at the interface.

2006011, Jun 8, 2006

Dec 7, 2004

11/005784

Jason Gonzalez - Fort Collins CO, US

H03K 19/003

326030000

Systems and methods for providing input/output signal termination with reduced power dissipation on an integrated circuit die are invented and disclosed. One embodiment comprises a method for reducing on die power dissipation while providing on die signal termination that includes receiving a termination reference voltage at a first input of an integrated circuit die, applying the first signal to a single termination element coupled in series between the first input and a receiver input to generate a common node reference voltage, receiving a second signal at a second input of the integrated circuit die, and coupling the second signal to the receiver input.

7053651, May 30, 2006

Sep 15, 2004

10/941187

Jason Gonzalez - Fort Collins CO, US

Avago Technologies General IP Pte. Ltd. - Singapore

G06F 7/38, H03K 19/173, H03K 3/00, H03B 1/00, H03L 7/06

326 38, 326 17, 326 21, 326 31, 327111, 327148, 327157

A CMOS switching circuit that includes a charge reservoir and a multiplexer connected to the charge reservoir. The multiplexer receives control signals from a delay line and a control signal line, and it delivers a switching signal to an output terminal. A first set of signals delivered to the control terminals of the multiplexer causes the charge reservoir to deliver charge to the output terminal, and a second set of signals delivered to the control terminals causes charging of the charge reservoir. With the charge reservoir, charge from falling signals is conserved and used to help rising signals at the output, reducing the power required to provide an output switching signal.