JAMIE JOSEPH LEVASSEUR
Pilots at Fisher Dr, Vancouver, WA

License number

Washington A2704223

Issued Date

Jun 2016

Expiration Date

Jun 2018

Professional information

Failsafe Display Of Frame Locked Graphics

US Patent:

6683604, Jan 27, 2004

Filed:

Apr 4, 2001

Appl. No.:

09/826493

Inventors:

Michael G. West - Portland OR
Jamie J. LeVasseur - Vancouver WA

Assignee:

Pixelworks, Inc. - Tualatin OR

International Classification:

G09G 502

US Classification:

345204, 345699

Abstract:

A system including a failsafe mechanism adapted to visually display frame locked digital image data and a method therefor. The system receives input image data at an input frame rate and/or input resolution. The packing circuit generates coded image data by compressing the input image data. An unpacking circuit decompresses the coded image and provides output image data to a display device at an output frame rate and/or output resolution.

Integrated Circuit Memory With A Bus Transceiver

US Patent:

6170041, Jan 2, 2001

Filed:

Sep 24, 1998

Appl. No.:

9/160499

Inventors:

Jamie Joseph LeVasseur - Vancouver WA
Joseph E. Herbst - Milpitas CA

Assignee:

Integrated Silicon Soulution, Inc. - Santa Clara CA

International Classification:

G06F 1200, G06F 1300

US Classification:

711149

Abstract:

A two port high speed integrated circuit memory device that includes a bus transceiver, a memory array and a decoder. The present invention provides a processor high speed access to the internal memory array via very low capacitive load address and data buses. The present invention also buffers a secondary bus to provide access to slower-speed local devices. The bus transceiver transfers address, data and control signals between the primary and secondary port and also couples signals to the internal memory array. The bus transceiver includes an input data bus, an output data bus, and an address and control bus. Each of these separate buses include a buffer at the primary and secondary port to minimize capacitive loading. The decoder in the two port memory device decodes memory chip select signals and control signals that define the operational mode of the device. To save power the present invention provides an operational mode in which primary bus signals are not reflected to the secondary bus unless the internal memory array is not selected by the chip selects.

System And Method For Aligning Multi-Channel Coded Data Over Multiple Clock Periods

US Patent:

6917366, Jul 12, 2005

Filed:

Apr 4, 2001

Appl. No.:

09/826538

Inventors:

Michael G. West - Portland OR, US
Jamie J. LeVasseur - Vancouver WA, US

Assignee:

Pixelworks, Inc. - Tualatin OR

International Classification:

G09G005/36

US Classification:

345558, 345505, 345559, 370537

Abstract:

A system and method is provided for aligning multi-channel coded data over multiple clock periods. Data is received through a plurality of data channels and stored in a plurality of latches or queues. Data is scanned to determine whether a valid data transition has occurred. Once a valid transition is detected on all of the plurality of data channels, data is substantially simultaneously read out of the latches or queues resulting in synchronized or aligned data being provided at the output.