James T Johnson
Massage Therapy in Boise, ID

2013034, Dec 26, 2013

Aug 26, 2013

14/010159

Joseph M. Jeddeloh - Shoreview MN, US
James B. Johnson - Boise ID, US

Micron Technology, Inc. - Boise ID

G06F 12/00

711167

A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of the memory device dice. The timing correction controls the timing of the read data or other signals by adjusting the timing of respective strobe signals, such as read strobe signals, that are applied to each of the memory device dice. The memory device dice may transmit read data to the memory device at a time determined by when it receives the respective strobe signals. The timing of each of the strobe signals is adjusted so that the read data or other signals from all of the memory device dice are received at the same time.

7627793, Dec 1, 2009

Feb 6, 2008

12/012840

James Brian Johnson - Boise ID, US

Micron Technology, Inc. - Boise ID

G11C 29/10, G11C 29/24

714720, 714712

A method and apparatus for determining the characteristics of a communications channel within a high speed memory system includes generating a first signal having a known and repeating pattern and generating a second signal having a pseudo-random pattern. The first and second signals are combined to produce a combined signal. The combined signal is transmitted over a communications channel of a memory system and received by the memory devices of the memory system. Each memory device removes the second signal from the received combined signal to produce a received first signal. Parameters associated with transmitting and receiving may be adjusted by examining the pattern of the received first signal to determine if it has the known pattern of the first signal. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

2006025, Nov 9, 2006

May 6, 2005

11/124002

James Johnson - Boise ID, US
Troy Manning - Meridian ID, US

G06F 13/00

711154000

A synchronous dynamic random access memory (“SDRAM”) device includes a pipelined write data path coupling data from a data bus to a DRAM array, and a pipelined read data path coupling read data from the array to the data bus. The SDRAM device also includes a bypass path allowing the write data in the write data path to be coupled directly to the read data path without first being stored in the DRAM array. The write data are preferably coupled through the write data path by issuing a write command to the DRAM device, and the read data are preferably coupled through the read data path by issuing a read command to the DRAM device. The memory array is inhibited from responding to these commands so that the write data are not stored in the array, and read data from the array are not coupled to the read data path.

7813192, Oct 12, 2010

Jun 22, 2009

12/489270

Joo S. Choi - Yongin, KR
James B. Johnson - Boise ID, US

Micron Technology, Inc. - Boise ID

G11C 7/00, G11C 7/10, G11C 8/18

365191, 365189011, 36518905, 365193, 365194, 365220, 365221, 3652335

A signal capture system and method is used to capture a data signal using a data strobe signal having a preamble of strobe signal transitions. The system includes a data latch circuit receiving the data signal. The data latch circuit is clocked by transitions of the data strobe signal to capture respective bits of data corresponding to the data signal. A decoder receives a memory command signal and generates a data start signal after a delay period from receiving the memory command signal if the command signal corresponds to a read or a write command. The receipt of read or write command signals is used by a control circuit to identify the start of valid read or write data signals. The control circuit then outputs the captured data signals responsive to the data start signal, thereby ignoring the transitions in the preamble of the data strobe signal.

7881149, Feb 1, 2011

Sep 1, 2009

12/551876

James Brian Johnson - Boise ID, US
Feng Lin - Boise ID, US
Brent Keeth - Boise ID, US

Micron Technology, Inc. - Boise ID

G11C 8/00

3652331, 36518916, 365194

A method and circuitry for improved write latency tracking in a SDRAM is disclosed. In one embodiment, a delay locked loop is used in the command portion of the write path, and receives the system clock as its reference input. The DLL includes a modeled delay which models the delay in transmission of the internal Write Valid signal and system clock distribution to the deserializers in the data path portion of the write path, which is otherwise controlled by the intermittently asserted write strobe signal. With the input distribution delay of the system clock (Clk) and the write strobe (WS) matched by design, the distributed system clock and Write Valid signal are synchronized to the WS distribution path by means of the DLL delay with reference to the system clock input to the DLL. By backing the distribution delay out of system clock as sent to the deserializers, the write valid signal is effectively synchronized with the write strobe, with the effect that data will be passed out of the deserializer circuitry to the memory array on time and consistent with the programmed write latency.

7346817, Mar 18, 2008

Aug 23, 2004

10/924306

James Brian Johnson - Boise ID, US

Micron Technology, Inc. - Boise ID

G11C 29/10, G11C 29/42

714720, 714728

A method and apparatus for determining the characteristics of a communications channel within a high speed memory system includes generating a first signal having a known and repeating pattern and generating a second signal having a pseudo-random pattern. The first and second signals are combined to produce a combined signal. The combined signal is transmitted over a communications channel of a memory system and is received by the memory devices of the memory system. Each memory device removes the second signal from the received combined signal to produce a received first signal. Parameters associated with transmitting and receiving may be adjusted by examining the pattern of the received first signal to determine if it has the known pattern of the first signal. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

7660187, Feb 9, 2010

Dec 8, 2008

12/329779

James Brian Johnson - Boise ID, US
Brent Keeth - Boise ID, US
Feng Dan Lin - Boise ID, US

Micron Technology, Inc. - Boise ID

G11C 8/00, H03L 7/06

36523317, 365194, 36523314, 365236, 327147, 327156, 327160

A method of controlling the output of data from a memory device includes deriving from an external clock signal a read clock and a control clock for operating an array of storage cells, both the read clock and the control clock each being comprised of clock pulses. A value is preloaded into one or both of a first counter located in the read clock domain and a second counter located in the control clock domain such that the difference in starting counts between the two counters is equal to a column address strobe latency (L) minus a synchronization (SP) overhead. A start signal is generated for initiating production of a running count of the read clock pulses in the first counter. The input of the start signal to the second counter is delayed so as to delay the initiation of a running count of the control clock pulses. A value of the second counter is held in response to a read command. The held value of the second counter is compared to a running count of the first counter; and data is output from the memory device with the read clock signal in response to the comparing.

7558133, Jul 7, 2009

Sep 14, 2007

11/901053

Joo S. Choi - Yongin, KR
James B. Johnson - Boise ID, US

Micron Technology, Inc. - Boise ID

G11C 7/00, G11C 7/10, G11C 8/18

365193, 36518903, 36518905, 3652335, 365220, 365221

A signal capture system and method is used to capture a data signal using a data strobe signal having a preamble of strobe signal transitions. The system includes a data latch circuit receiving the data signal. The data latch circuit is clocked by transitions of the data strobe signal to capture respective bits of data corresponding to the data signal. A decoder receives a memory command signal and generates a data start signal after a delay period from receiving the memory command signal if the command signal corresponds to a read or a write command. The receipt of read or write command signals is used by a control circuit to identify the start of valid read or write data signals. The control circuit then outputs the captured data signals responsive to the data start signal, thereby ignoring the transitions in the preamble of the data strobe signal.

7251762, Jul 31, 2007

Apr 19, 2005

11/109535

Chris Martin - Boise ID, US
James Brian Johnson - Boise ID, US
Troy Manning - Meridian ID, US
Brent Keeth - Boise ID, US

Micron Technology, Inc. - Boise ID

G01R 31/28

714724, 714 30, 714734, 703 28, 324754, 365201

Through addressing circuitry, a sampling circuit can choose a unique internal node/signal on an encapsulated/packaged chip to be output to one or more drivers. The chosen signals available at the target node are directed either through a select circuit to an output pin, or directly to an output pin. In a preferred mode, decode circuits used to select a unique node are serially connected, allowing for a large number of signals to be made available for analyzing without a large impact on circuit layout.

8169841, May 1, 2012

Jan 23, 2009

12/358977

James Brian Johnson - Boise ID, US
Paul A. LaBerge - Shoreview MN, US
Jake Klier - Blaine MN, US

Micron Technology, Inc. - Boise ID

G11C 7/00

365193, 365194, 3652331, 36523313

A strobe signal is received in a device and execution of an operation in the device is delayed when the strobe signal includes a preamble. Additional apparatus, systems, and methods are disclosed.