DR. JAMES RUSSEL VAN NORMAN, MD
Psychiatric at Collier St, Austin, TX

7620661, Nov 17, 2009

Oct 27, 2005

11/260623

David William Mehaffy - Austin TX, US
James William Van Fleet - Austin TX, US

International Business Machines Corporation - Armonk NY

G08F 12/00, G06F 17/30

707202, 707200

A method for substantially reducing the latency of the database (DB) logging process by removing the agent notification requirement from the DB logger and allowing the DB logger to proceed to the next commit process without the latency of providing each waiting agent a notification that the agent continue their respective processes. When an agent commits a change to persistent storage of the database, the request is received by the logger, which performs the update to the persistent storage. A list of agents waiting on the completion of the commit process is compiled by the logger. The list of agents is provided to and provided to the next committing agent. The next committing agent then notifies the waiting agents that they are able to proceed with their respective processing. The logger may immediately perform the next update to persistent memory without utilizing a substantial amount of time notifying the waiting agents.

6825847, Nov 30, 2004

Nov 30, 2001

10/006409

Steven E. Molnar - Chapel Hill NC
Bengt-Olaf Schneider - Carmel NY
John Montrym - Cupertino CA
James M. Van Dyke - Austin TX
Stephen D. Lew - Sunnyvale CA

NVIDIA Corporation - Santa Clara CA

G09G 900

345555, 345611

A system and method are provided for the compression of pixel data for communicating the same with a frame buffer. Initially, a plurality of samples is received. It is first determined whether the samples are reducible, in that a single sample value can take the place of a plurality of sample values. If it is determined that the samples are capable of being reduced, the samples are reduced. Reduction is a first stage of compression. It is then determined whether the samples are capable of being compacted. The samples are then compacted if it is determined that the samples are capable of being compacted. Compaction is a second stage of compression. The samples are then communicated with a frame buffer, in compressed form, if possible, in uncompressed form if not. Subsequent reading of frame buffer data takes advantage of the smaller transfer size of compressed data. Compressed data is uncompacted and expanded as necessary for further processing or display.

7448036, Nov 4, 2008

May 2, 2002

10/138890

Larry Bert Brenner - Austin TX, US
Mysore Sathyanarayana Srinivas - Austin TX, US
James W. Van Fleet - Austin TX, US

International Business Machines Corporation - Armonk NY

G06F 9/46

718103

A system and method for thread scheduling with a weak preemption policy is provided. The scheduler receives requests from newly ready work. The scheduler adds a “preempt value” to the current work's priority so that it is somewhat increased for preemption purposes. The preempt value can be adjusted in order to make it more, or less, difficult for newly ready work to preempt the current work. A “less strict” preemption policy allows current work to complete rather than interrupting the current work and resume it at a later time, thus saving system overhead. Newly ready work that is queued with a better priority than the current work is queued in a favorable position to be executed after the current work is completed but before other work that has been queued with the same priority of the current work.

5790846, Aug 4, 1998

Apr 18, 1996

8/634712

Bruce Gerard Mealey - Austin TX
James William Van Fleet - Austin TX
Michael Stephen Williams - Austin TX

International Business Machines Corporation - Armonk NY

G06F 946

395591

An exception handler for a computer system, particularly for performance monitoring facilities, employs implementation-dependent steps executed from a kernel extension which is more application-level than kernel level. The implementation-independent kernel is involved only at very minimum level for a prologue to the exception handling routine. First, a kernel extension registers an exception with the processor by storing the address of a pointer to a first-level interrupt handler; this address is stored in a location in kernel data storage, in non-paged memory. When an exception condition is reached, state is saved and the address location is checked to see if an exception has been registered. If so, the address is used to go to the first-level interrupt handler, which is at the kernel extension level. The first-level interrupt handler may access a second-level interrupt handler.

7340577, Mar 4, 2008

May 29, 2002

10/158316

James M. Van Dyke - Austin TX, US
John S. Montrym - Cupertino CA, US

NVIDIA Corporation - Santa Clara CA

G06F 13/26

711169, 711167

A method and system for efficiently executing reads after writes in a memory. The system includes a memory controller and a memory core interfacing with the memory controller. The memory operates with a read data latency and a similar write data latency, and the memory immediately processes a read in a read-after-write situation. The system further includes a control circuit for controlling the memory and detecting an address collision between the read and a previously issued write and, in response thereto, stalling the memory by delaying issuance of the read to the memory until after the previously issued write completes.

2008027, Oct 30, 2008

Jul 7, 2008

12/168265

Larry Bert Brenner - Austin TX, US
Mysore Sathyanarayana Srinivas - Austin TX, US
James W. Van Fleet - Austin TX, US

International Business Machines Corporation - Armonk NY

G06F 9/46

718103

Thread scheduling with a weak preemption policy is provided. The scheduler receives requests from newly ready work. The scheduler adds a “preempt value” to the current work's priority so that it is somewhat increased for preemption purposes. The preempt value can be adjusted in order to make it more, or less, difficult for newly ready work to preempt the current work. A “less strict” preemption policy allows current work to complete rather than interrupting the current work and resume it at a later time, thus saving system overhead. Newly ready work that is queued with a better priority than the current work is queued in a favorable position to be executed after the current work is completed but before other work that has been queued with the same priority of the current work.

7318220, Jan 8, 2008

Mar 11, 2004

10/798905

David William Mehaffy - Austin TX, US
James William Van Fleet - Austin TX, US

International Business Machines Corporation - Armonk NY

G06F 9/44

717127, 717128, 707 8, 710200

A system and method is provided for measuring lock usage in a non-intrusive manner. Measurements are performed only when a lock is contended. When a lock is requested and the lock is available (i. e. , is not contended), the only data gathered is a counter that is incremented to keep track of the number of times the particular lock was requested. When a lock is contended, an operating system trace hook is requested. The trace hook records data such as the timestamp that the requestor requested the lock, the request count, a stack traceback to identify the function corresponding to the requestor, and the address of the lock that was requested. Post-operative processing analyzes the recorded trace hook data to identify contended locks and processes that may not be efficiently using locks.

2011007, Mar 31, 2011

Sep 21, 2010

12/887432

James M. VAN DYKE - Austin TX, US

G06F 12/00, G06F 12/10

711 5, 711105, 711E12078, 711E12058

One embodiment of the present invention sets forth a technique for computing dynamic random access memory (DRAM) addresses from linear physical addresses for memory subsystems implementing integral power of two virtual page sizes, and an arbitrary number of available partitions. Each DRAM address comprises a row address, column address, bank address, and partition address. The linear physical address is used to generate to the DRAM address in units of a DRAM bank size. Address scrambling may be implemented to overcome transient access contention to specific DRAM pages by multiple client modules.

7932912, Apr 26, 2011

Nov 2, 2006

11/556148

James M. Van Dyke - Austin TX, US

Nvidia Corporation - Santa Clara CA

G06F 12/02, G06F 12/10, G06T 9/00

345544, 345568, 345555

A graphics system has virtual memory and a partitioned graphics memory that supports having an non-power of two number of dynamic random access memories (DRAMs). The graphics system utilizes page table entries to support addressing Tag RAMs used to store tag bits indicative of a compression status.

5764884, Jun 9, 1998

Oct 31, 1996

8/741734

James William Van Fleet - Austin TX

International Business Machines Corp. - Armonk NY

G06F 1128

39518314

A method and apparatus for monitoring the execution of a procedure having multiple exit points without modifying the software via breakpoints. The starting address of the procedure is loaded into an Instruction Address Break Register (IABR). Upon execution of the starting address the IABR raises an exception. The processing of the exception is used to implement a counting routine and for loading the IABR with the address of the calling party via the Link Register. Upon execution of the address of the calling party, the IABR once again raises an exception. The processing of the second exception is used for stopping the counter and performing any related analysis.