James Richard Wasson
Engineering at Kentucky Ln, Tempe, AZ
License number
Louisiana EI.0015559
Issued Date
Jun 21, 1994
Expiration Date
Sep 30, 2006
Category
Civil Engineer
Address
Address
1921 E Kentucky Ln, Tempe, AZ 85284
Professional information
Method Of Patterning Photoresist On A Wafer Using A Transmission Mask With A Carbon Layer
US Patent:
6939650, Sep 6, 2005
Filed:
Jan 17, 2003
Appl. No.:
10/346623
Inventors:
James R. Wasson - Tempe AZ, US
Pawitter Mangat - Gilbert AZ, US
Pawitter Mangat - Gilbert AZ, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
G03F009/00, G03C005/00
US Classification:
430 5, 430322, 430323, 430324
Abstract:
A photoresist layer on a semiconductor wafer is patterned using a mask with an absorbing layer that has been repaired by using an additional light-absorbing carbon layer that collects ions that are used in the repair process. After the repair has been completed, the ions that are present in the carbon layer are removed by removing the portion of the carbon layer that is not covered by the absorbing layer. Thus, the absorbing layer, which contains the pattern that is to be exposed on the photoresist layer, also acts as a mask in the removal of the portion of the carbon layer that contains the ions. Thereby the ions that are opaque at the particular wavelength being used are removed from the areas where light is intended to pass through the mask to the photoresist. The buffer layer is made absorbing to avoid problems with reflections at interfaces thereof.
Method Of Patterning Photoresist On A Wafer Using A Reflective Mask With A Multi-Layer Arc
US Patent:
7026076, Apr 11, 2006
Filed:
Mar 3, 2003
Appl. No.:
10/377847
Inventors:
James R. Wasson - Tempe AZ, US
Pawitter Mangat - Gilbert AZ, US
Pawitter Mangat - Gilbert AZ, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
G01F 9/00
US Classification:
430 5
Abstract:
A patterned reflective semiconductor mask () uses a multiple layer ARC () overlying an absorber stack () that overlies a reflective substrate (). The absorber stack has more than one layer and an upper layer of the absorber stack has a predetermined metal. The multiple layer ARC overlying the upper layer of the absorber stack has layers of nitrogen, oxygen and nitrogen combined with the predetermined metal of the upper layer of the absorber stack. The oxygen layer in the ARC has less metallic properties than the nitrogen layers therein. In one form, an overlying dielectric layer () is positioned on the multiple layer ARC to increase light interference. The ARC provides wide bandwidth inspection contrast for extreme ultra-violet (EUV) reticles.
Method Of Patterning Photoresist On A Wafer Using An Attenuated Phase Shift Mask
US Patent:
6875546, Apr 5, 2005
Filed:
Mar 3, 2003
Appl. No.:
10/377844
Inventors:
James R. Wasson - Tempe AZ, US
Pawitter Mangat - Gilbert AZ, US
Pawitter Mangat - Gilbert AZ, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
G03F009/00
US Classification:
430 5
Abstract:
An attenuated phase shift mask (or ) includes a substrate (or ) and an attenuation stack (or ) overlying the substrate. The attenuation stack includes a chromium layer or ruthenium layer (or ) overlying the substrate, a tantalum silicon oxide layer (or ) overlying the chromium layer or the ruthenium layer, and a tantalum silicon nitride layer (or ) overlying the tantalum silicon oxide layer. The attenuation stack may also include a layer () between the substrate () and the chromium or ruthenium layer (). In one embodiment, this layer is a portion of the substrate. The attenuation stack is used to pattern photoresist () on a semiconductor wafer. In one embodiment, portions of the substrate adjacent the attenuation stack has a transmission of greater than 90 percent and the attenuation stack has a transmission of 5 to 20 percent at the exposure wavelength. In one embodiment, an inspection contrast between the substrate and the attenuation stack at an inspection wavelength is greater than 75 percent.
Method Of Patterning Photoresist On A Wafer Using A Reflective Mask With A Multi-Layer Arc
US Patent:
7378197, May 27, 2008
Filed:
Nov 7, 2005
Appl. No.:
11/267983
Inventors:
James R. Wasson - Tempe AZ, US
Pawitter Mangat - Gilbert AZ, US
Pawitter Mangat - Gilbert AZ, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
G03F 1/00
US Classification:
430 5
Abstract:
A patterned reflective semiconductor mask uses a multiple layer ARC overlying an absorber stack that overlies a reflective substrate. The absorber stack has more than one layer and an upper layer of the absorber stack has a predetermined metal. The multiple layer ARC overlying the upper layer of the absorber stack has layers of nitrogen, oxygen and nitrogen combined with the predetermined metal of the upper layer of the absorber stack. The oxygen layer in the ARC has less metallic properties than the nitrogen layers therein. In one form, an overlying dielectric layer is positioned on the multiple layer ARC to increase light interference. The ARC provides wide bandwidth inspection contrast for extreme ultra-violet (EUV) reticles.
Method For Fabricating A Mask Using A Hardmask And Method For Making A Semiconductor Device Using The Same
US Patent:
7074527, Jul 11, 2006
Filed:
Sep 23, 2003
Appl. No.:
10/668432
Inventors:
Bing Lu - Gilbert AZ, US
James R. Wasson - Tempe AZ, US
James R. Wasson - Tempe AZ, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
G01F 9/00
US Classification:
430 5
Abstract:
A bilayer hardmask is used to manufacture a mask , which is can be implemented to pattern a resist on a semiconductor wafer. In one embodiment, the bilayer hardmask has two layers: a first hardmask layer and a second hardmask layer. The first hardmask layer may be carbon and can be etched selective to the overlying second hardmask layer and an underlying absorber structure. In one embodiment, the second hardmask layer is a transparent layer of SiON, SiN, or SiO. The bilayer hardmask allows for a thinner resist to be used during fabrication of the mask.
High Density Capacitor Array Patterns
US Patent:
2013014, Jun 13, 2013
Filed:
Feb 5, 2013
Appl. No.:
13/759109
Inventors:
James R. Wasson - Tempe AZ, US
Assignee:
MEDTRONIC, INC. - Minneapolis MN
International Classification:
H01G 4/33
US Classification:
361304, 216 11, 216 6
Abstract:
A thin-film device system includes a substrate and a plurality of pillars. The plurality of pillars project from a surface of the substrate. Each of the plurality of pillars have a perimeter that includes at least four protrusions that define at least four recessed regions between the at least four protrusions. Each of the at least four recessed regions of each of the plurality of pillars receives one protrusion from an adjacent one of the plurality of pillars. A thin-film device is fabricated over the plurality of pillars.
High Density Capacitor Array Patterns
US Patent:
8395880, Mar 12, 2013
Filed:
Mar 30, 2010
Appl. No.:
12/750301
Inventors:
James R. Wasson - Tempe AZ, US
Assignee:
Medtronic, Inc. - Minneapolis MN
International Classification:
H01G 4/00
US Classification:
3613011, 3613012, 361312, 3613015, 361305, 3613062
Abstract:
A thin-film device system includes a substrate and a plurality of pillars. The plurality of pillars project from a surface of the substrate. Each of the plurality of pillars have a perimeter that includes at least four protrusions that define at least four recessed regions between the at least four protrusions. Each of the at least four recessed regions of each of the plurality of pillars receives one protrusion from an adjacent one of the plurality of pillars. A thin-film device is fabricated over the plurality of pillars.
Inductive Coil Device On Flexible Substrate
US Patent:
8543190, Sep 24, 2013
Filed:
Jul 30, 2010
Appl. No.:
12/847307
Inventors:
James R. Wasson - Tempe AZ, US
Clark B. Norgaard - Phoenix AZ, US
Bruce C. Fleischhauer - Chandler AZ, US
Michael F. Mattes - Chandler AZ, US
Randal C. Schulhauser - Phoenix AZ, US
Clark B. Norgaard - Phoenix AZ, US
Bruce C. Fleischhauer - Chandler AZ, US
Michael F. Mattes - Chandler AZ, US
Randal C. Schulhauser - Phoenix AZ, US
Assignee:
Medtronic, Inc. - Minneapolis MN
International Classification:
A61B 5/05, H01F 27/28
US Classification:
600424, 336180
Abstract:
A device includes a flexible substrate, N coiled conductors, and a plurality of folding regions. The N coiled conductors are deposited on the flexible substrate and connected in series by conductive interconnects. N is greater than 1. Each of the folding regions is defined by a separation distance between adjacent ones of the N coiled conductors. The conductive interconnects traverse the folding regions between the N coiled conductors to connect the N coiled conductors in series. The flexible substrate is folded such that the N coiled conductors form a stack of N coiled conductors.