JAMES R GARRETT, JR
Electrician at Tangle Brush Dr, Spring, TX

5068649, Nov 26, 1991

Oct 14, 1988

7/258269

James H. Garrett - Spring TX

Compaq Computer Corporation - Houston TX

G09G 318

340793

A method and apparatus are disclosed which provide a means for both spatially and temporally resolving the on/off states of a two-state display device such as a liquid cystal display to provide apparent shades of gray. A particular feature of this method is that the cycling between on and off states is not performed in a discernible pattern. Rather, a pseudo-random pattern is utilized which repeats only after many cycles. Additionally, when the method disclosed herein is utilized, adjacent pixels, when selected to display the same shade of gray, do not cycle on and off in synchronization, but rather utilize out-of-phase cycling patterns. This spatial resolution reduces perceived flicker in the display and provides a more stable image. In one embodiment, eight shades of gray are provided. The shades are generated by cycling individual pixels such that when averaged over time, they are: always off; on 20% of the time; 33% of the time; 40% of the time; 60% of the time; 67% of the time; 80% of the time; or, on at all times.

5245328, Sep 14, 1993

Oct 15, 1990

7/597814

James H. Garrett - Spring TX

Compaq Computer Corporation - Houston TX

G09G 300

345149

A method and apparatus are disclosed which provide a means for both spatially and temporarily resolving the on/off states of a two-state display device such as a liquid crystal display to provide apparent shades of gray. A particular feature of this method is that the cycling between on and off states is not performed in a single, repetitive pattern. Rather, a pattern is utilized which repeats only after many cycles. Additionally, when the 10 method disclosed herein is utilized, adjacent pixels, when selected to display the same shade of gray, do not cycle on and off in synchronization, but rather utilize out-of-phase cycling patterns. This spatial resolution reduces perceived flicker in the display and provides a more stable image. In one embodiment, sixteen shades of gray are provided. The shades are generated by cycling individual pixels such that when averaged over time, the duty cycles of such cycling are 0, 1/9, 1/7, 1/5, 2/7, 1/3, 2/5, 7/15, 8/15, 3/5, 2/3, 5/7, 4/5, 6/7, 8/9 and 1.

5534889, Jul 9, 1996

Sep 10, 1993

8/119422

Daniel B. Reents - Spring TX
Patrick R. Cooper - Houston TX
James H. Garrett - Spring TX
Philip J. McKenzie - Houston TX

Compaq Computer Corporation - Houston TX

G09G 500

345132

A liquid crystal display (LCD) panel which has its contrast controlled through the use of a pulse width modulation (PWM) circuit contained in the video controller and a contrast control circuit. In response to a particular video refresh mode, the PWM circuit modulates the pulse width of a signal that is an input to the contrast control circuit. The pulse width is changed by the use of a base contrast register and two offset registers. Depending on the video mode, the base register is used alone or is combined with one of the offset registers to provide a signal to indicate the duty cycle of the signal. The pulse width modulated signal is converted to a DC bias contrast voltage which is provided to the LCD panel.

5142247, Aug 25, 1992

Aug 6, 1991

7/741083

Henry F. Lada - Houston TX
Hung Q. Le - Houston TX
James H. Garrett - Spring TX
John M. Gromala - Houston TX

Compaq Computer Corporation - Houston TX

H03L 7099, H03L 718

331 14

A phase-locked loop (PLL) clock generator circuit which is capable of changing the frequency of its outpt clock signal in a stable fashion. Selection of the frequency of the output clock signal is made by way of a selectable frequency divider coupled between the reference clock signal and an input of the PLL, with another frequency divider in the feedback loop of the PLL; each of these frequency dividers are selectable according to a signal on a select bus, translated by way of a ROM look-up table. The circuit also includes a multiplexer having a first input coupled to the PLL output, and a second input coupled to a stable clock signal, for example to the referenc clock signal or to the output of a fixed frequency PLL. The conrol input of the multiplexer is controlled by a state machine which monitors the select bus. Responsive to detection of a transition of the select bus, indicating a new frequency, the state machine issues a pulse to the control input of the multiplexer to cause it to select the stable clock signal for sufficient time to allow the PLL to acquire and lock onto the new frequency, after which the multiplexer again selects the PLL output as the output clock signal.