James R Edwards
Plumbers at Rdg Crk Ct, Longmont, CO

6154798, Nov 28, 2000

Feb 16, 1999

9/250596

Richard S. Lin - Houston TX
David J. Maguire - Spring TX
James R. Edwards - Longmont CO
David J. Delisle - Spring TX

Compaq Computer Corporation - Houston TX

G06F 1312

710 72

A method for hot docking and hot undocking a portable computer and a docking station. The portable computer and docking station are physically coupled via a shared PCI bus and an expansion connector. Varying length pins in the expansion connector generate docking and undocking handshaking signals used by microcontrollers in the portable computer and docking station. The portable computer and docking station are functionally connected via low onresistance switches located in the portable computer. Following a docking event, closure of the switches connects the portion of the shared PCI bus in the docking station with the PCI bus in the portable computer. When the switches are open, the PCI busses are functionally isolated. Both the portable computer and the docking station also include a local arbiter for arbitrating and granting bus control requests from devices coupled to the shared PCI bus. These local arbiters may be placed into an idled state by either the operating system (through system BIOS) or by the microcontrollers.

5943500, Aug 24, 1999

Jul 19, 1996

8/684485

David J. Maguire - Spring TX
James R. Edwards - Longmont CO

Compaq Computer Corporation - Houston TX

G06F 946

395733

An apparatus handles long latency interrupt signals in a computer which posts I/O write operations. The apparatus includes a posting buffer for posting write operations and circuitry for ensuring that End-of-Interrupt (EOI) write operations (and other interrupt controller directed I/O operations) are properly synchronized to prevent false interrupts from reaching the processor. Upon receipt of the EOI write operation, the apparatus verifies that the posting buffer is empty before it imposes a pre-determined delay to ensure sufficient time for the cleared the interrupt signal to be transmitted over the interrupt serial bus. Next, the apparatus checks the interrupt serial bus for activities. If the interrupt serial bus is idle, the EOI write operation is issued to the interrupt controller. Alternatively, the apparatus waits until the serial bus becomes inactive for two back-to-back cycles before allowing the EOI write operation to be issued to the interrupt controller.

5761460, Jun 2, 1998

Jul 19, 1996

8/684490

Gregory N. Santos - Cypress TX
David J. Maguire - Spring TX
William C. Hallowell - Spring TX
James R. Edwards - Longmont CO

Compaq Computer Corporation - Houston TX

G06F 1300

395309

A dual-master data storage interface is disclosed which flexibly configures and connects data storage drives in the portable computer to optimize performance when the portable computer is operating in a stand-alone mode and to optimize accessibility to additional data storage drives when the portable computer is docked with an expansion unit. When the portable computer operates as a stand-alone unit (i. e. , not docked to the expansion unit), each drive on the portable is configured to operate as a master drive to optimize performance. When the portable computer docks with the expansion unit, the first channel on the portable computer is connected via switches to both drives of the portable computer, while the second channel on the portable computer is disconnected. Further, the first data storage drive is configured as a master and the second data storage drive is configured as a slave drive on the portable computer side. Correspondingly, the drives located on the expansion base unit are reconfigured and remapped as master and slave drives on the second channel on the expansion base unit, while the first channel on the expansion base unit is disconnected.

5781748, Jul 14, 1998

Jul 19, 1996

8/671316

Gregory N. Santos - Cypress TX
David J. Maguire - Spring TX
Dwight D. Riley - Houston TX
James R. Edwards - Longmont CO

Compaq Computer Corporation - Houston TX

H01J 1300

395308

A computer system having an expansion base for docking a portable portion of the computer system includes a bridge circuit for adaptively decoding addresses on a bus based on the docking status. Both the expansion base and the portable portion include the bridge circuit for passing cycles from a peripheral component interconnect (PCI) bus to an industry standard architecture (ISA) bus. The bridge includes internal devices and configuration registers for controlling the decoding. Bus cycles intended for internal devices and external devices connected to each respective ISA bus of the bridge circuits are positively decoded. Cycles not positively decoded and claimed are subtractively decoded by one of the bridge circuits depending on the docking status.

5864688, Jan 26, 1999

Jul 19, 1996

8/684584

Gregory N. Santos - Cypress TX
David J. Maguire - Spring TX
Dwight D. Riley - Houston TX
James R. Edwards - Longmont CO

Compaq Computer Corporation - Houston TX

G06F 1200

395309

A computer system having an expansion base for docking a portable portion of the computer system includes a bridge circuit for adaptively decoding addresses on a bus based on the docking status. Both the expansion base and the portable portion include the bridge circuit for passing cycles from a peripheral component interconnect (PCI) bus to an industry standard architecture (ISA) bus. The bridge includes internal devices and configuration registers for controlling the decoding. Bus cycles intended for internal devices and external devices connected to each respective ISA bus of the bridge circuits are positively decoded. Cycles not positively decoded and claimed are subtractively decoded by one of the bridge circuits depending on the docking status.

5721935, Feb 24, 1998

Feb 18, 1997

8/801200

Todd J. DeSchepper - Houston TX
James R. Reif - Houston TX
James R. Edwards - Longmont CO
Michael J. Collins - Tomball TX
John E. Larson - Katy TX

Compaq Computer Corporation - Houston TX

G06F 132

395750

A power management circuit for managing low power modes in a computer system, which implements four power modes, from highest power consumption to lowest power consumption: RUN mode, SLEEP mode, IDLE mode, and STANDBY mode. The computer system includes a PCI bus and an ISA bus, with a CPU-PCI bridge to connect the host bus and the PCI bus and a PCI-ISA bridge to connect the PCI bus and the ISA bus. The power management circuit transitions from SLEEP mode to IDLE mode by first determining if the CPU-PCI bridge is parked on the PCI bus and if it is in SLEEP mode. The power management circuit then waits for one refresh period and for all internal queues to empty before checking again to determine if the CPU-PCI bridge is still parked on the PCI bus and if it is still in SLEEP mode. If true, the CPU-PCI bridge transitions to IDLE mode. The power management circuit also performs low power refresh cycles when it is in IDLE or STANDBY mode.

5954809, Sep 21, 1999

Jul 19, 1996

8/684412

Dwight D. Riley - Houston TX
James R. Edwards - Longmont CO
David J. Maguire - Spring TX

Compaq Computer Corporation - Houston TX

G06F 13368

710119

An arbitration scheme for a computer system having multiple arbiters for arbitrating access to a plurality of buses. In the preferred embodiment, a computer system is divided into a detachable laptop portion and an expansion base unit coupled through a shared PCI bus. Each of the two portions of the computer system includes separate PCI arbitration circuitry for arbitrating requests for the PCI bus from potential PCI and ISA bus masters. Included within the laptop portion of the computer system is a top level arbiter that determines whether the PCI arbiter in the laptop or expansion base unit has access to the PCI bus. Either PCI arbiter normally must receive a grant from the top level arbiter before it runs a cycle. While the laptop computer is docked, the top level arbiter selects between the PCI arbiters on an essentially time multiplexed basis. While the expansion base and laptop computer are undocked, the top level arbiter grants bus access to the laptop PCI arbiter.

8054676, Nov 8, 2011

Aug 18, 2008

12/193365

Kevin B. Tanguay - Thornton CO, US
James R. Edwards - Longmont CO, US
David W. Frodin - Longmont CO, US
Marshall A. Dawson - Longmont CO, US
Scott B. Hoot - Longmont CO, US

Advanced Micro Devices, Inc. - Sunnyvale CA

G11C 11/24

365149, 365191, 36523313, 711105

A memory system () includes a plurality of memory devices () adapted to be coupled to an interface (), an indicator () for indicating a type of the plurality of memory devices (), and an override circuit () having a first terminal adapted to be coupled to the interface (), a second terminal coupled to the plurality of the memory devices (), and a control input for receiving a control signal. The override circuit () is responsive to the control signal to alter an operation of the memory system ().

5774680, Jun 30, 1998

Dec 11, 1995

8/570394

Christopher C. Wanner - Tomball TX
Jeffrey C. Stevens - Spring TX
Robert A. Lester - Houston TX
Dwight D. Riley - Houston TX
David J. Maguire - Spring TX
James Edwards - Longmont CO

Compaq Computer Corporation - Houston TX

G06F 1300

395290

A computer system having separate, yet compatible DMA controllers on a bus. Each DMA controller for controlling at least one DMA channel, each DMA controller having an independent set of registers for performing DMA operations and a configuration register for indicating channel status and designation. A DMA master for compatibly communicating with a processor and for initializing and communicating with the multiple DMA controllers.