JAMES PAUL MYERS
Pilots at 165 Pl, Woodinville, WA
License number
Washington A5118459
Issued Date
Apr 2015
Expiration Date
Apr 2017
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
14545 165Th Pl NE, Woodinville, WA 98072
Professional information
Latching Inputs And Enabling Outputs On Bidirectional Pins With A Phase Locked Loop (Pll) Lock Detect Circuit
US Patent:
5764714, Jun 9, 1998
Filed:
Aug 20, 1996
Appl. No.:
8/700249
Inventors:
Galen E. Stansell - Kirkland WA
J. Kenneth Fox - Bothell WA
Eric N. Mann - Issaquah WA
James P. Myers - Woodinville WA
Timothy V. Wright - Kirkland WA
J. Kenneth Fox - Bothell WA
Eric N. Mann - Issaquah WA
James P. Myers - Woodinville WA
Timothy V. Wright - Kirkland WA
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
G06F 1300
US Classification:
375377
Abstract:
A circuit for latching inputs and enabling outputs on a bidirectional pin using a PLL lock detect circuit is disclosed. A PLL lock detect circuit generates an active lock control signal when an output reference signal is phase locked relative to an input reference signal applied to a phase locked loop (PLL) circuit. A latch and enable circuit is responsive to this lock control signal to latch the input signal (off of the pin), and, thereafter, enable output of an output signal onto the bidirectional pin. The latch and enable circuit includes a data latch to store the input signal when the lock control signal goes to an active state. The latch and enable circuit also includes a delay circuit to delay the lock control signal to produce a delayed lock control signal, and a tristateable output driver that is tristated when the delayed lock control signal is inactive, but, operates to pass (i. e. , enable) the output signal to the bidirectional pin when the delayed lock control signal is active.
Memory Architecture Having A Reference Current Generator That Provides Two Reference Currents
US Patent:
7969804, Jun 28, 2011
Filed:
Dec 24, 2008
Appl. No.:
12/343617
Inventors:
Ryan T. Hirose - Colorado Springs CO, US
Fredrick Jenne - Sunnyvale CA, US
Vijay Srinivasaraghavan - Colorado Springs CO, US
Igor G. Kouznetsov - San Jose CA, US
Paul Fredrick Ruths - Woodland Park CO, US
Cristinel Zonte - Colorado Springs CO, US
Bogdan Georgescu - Colorado Springs CO, US
Leonard Vasile Gitlan - Colorado Springs CO, US
James Paul Myers - Woodinville WA, US
Fredrick Jenne - Sunnyvale CA, US
Vijay Srinivasaraghavan - Colorado Springs CO, US
Igor G. Kouznetsov - San Jose CA, US
Paul Fredrick Ruths - Woodland Park CO, US
Cristinel Zonte - Colorado Springs CO, US
Bogdan Georgescu - Colorado Springs CO, US
Leonard Vasile Gitlan - Colorado Springs CO, US
James Paul Myers - Woodinville WA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
G11C 7/00
US Classification:
365206, 365207, 365208, 36518906, 365210
Abstract:
A memory architecture is provided with an array of non-volatile memory cells arranged in rows and columns, and a sense amplifier coupled to at least one column within the array for sensing a data bit stored within one of the non-volatile memory cells. In order to provide accurate sensing, a reference current generator is provided and coupled to the sense amplifier. The reference current generator provides a first reference current having adjustable magnitude and adjustable slope, and a second reference current having adjustable magnitude, but constant slope. The first reference current is supplied to the sense amplifier for sensing the data bit. The second reference current is supplied to a control block for generating clock signals used to control sense amplifier timing.
Memory Architecture Having Two Independently Controlled Voltage Pumps
US Patent:
8542541, Sep 24, 2013
Filed:
Feb 28, 2012
Appl. No.:
13/407660
Inventors:
Ryan T. Hirose - Colorado Springs CO, US
Fredrick Jenne - Sunnyvale CA, US
Vijay Srinivasaraghavan - Colorado Springs CO, US
Igor G. Kouznetsov - San Jose CA, US
Paul Fredrick Ruths - Woodland Park CO, US
Cristinel Zonte - Colorado Springs CO, US
Bogdan Georgescu - Colorado Springs CO, US
Leonard Vasile Gitlan - Colorado Springs CO, US
James Paul Myers - Woodinville WA, US
Fredrick Jenne - Sunnyvale CA, US
Vijay Srinivasaraghavan - Colorado Springs CO, US
Igor G. Kouznetsov - San Jose CA, US
Paul Fredrick Ruths - Woodland Park CO, US
Cristinel Zonte - Colorado Springs CO, US
Bogdan Georgescu - Colorado Springs CO, US
Leonard Vasile Gitlan - Colorado Springs CO, US
James Paul Myers - Woodinville WA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
G11C 16/04
US Classification:
36518529, 36518518
Abstract:
In embodiments described herein, a memory architecture has an array of non-volatile memory cells and a pair of independently controlled voltage pumps. The pair of voltage pumps is coupled for supplying both positive and negative voltage biases to the memory array during program and erase operations, such that a sum of the magnitudes of the positive and negative voltage biases is applied across a storage node of an accessed memory cell.
Memory Architecture Having Two Independently Controlled Voltage Pumps
US Patent:
8125835, Feb 28, 2012
Filed:
Dec 24, 2008
Appl. No.:
12/343658
Inventors:
Ryan T. Hirose - Colorado Springs CO, US
Fredrick Jenne - Sunnyvale CA, US
Vijay Raghavan - Colorado Springs CO, US
Igor G. Kouznetsov - San Jose CA, US
Paul Fredrick Ruths - Woodland Park CO, US
Cristinel Zonte - Colorado Springs CO, US
Bogdan I. Georgescu - Colorado Springs CO, US
Leonard Vasile Gitlan - Colorado Springs CO, US
James Paul Myers - Woodinville WA, US
Fredrick Jenne - Sunnyvale CA, US
Vijay Raghavan - Colorado Springs CO, US
Igor G. Kouznetsov - San Jose CA, US
Paul Fredrick Ruths - Woodland Park CO, US
Cristinel Zonte - Colorado Springs CO, US
Bogdan I. Georgescu - Colorado Springs CO, US
Leonard Vasile Gitlan - Colorado Springs CO, US
James Paul Myers - Woodinville WA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
G11C 16/06, G11C 5/14
US Classification:
36518529, 36518518, 365126
Abstract:
In embodiments described herein, a memory architecture has an array of non-volatile memory cells and a pair of independently controlled voltage pumps. The pair of voltage pumps is coupled for supplying both positive and negative voltage biases to the memory array during program and erase operations, such that a sum of the magnitudes of the positive and negative voltage biases is applied across a storage node of an accessed memory cell.