JAMES PARK COLEMAN, PT
Physical Therapy in Mesa, AZ
License number
Arizona 6982
Category
Restorative Service Providers
Type
Physical Therapist
Address
Address
2
4566 E INVERNESS 101, Mesa, AZ 85206
49 W Canyon Rock Rd, Queen Creek, AZ 85243
49 W Canyon Rock Rd, Queen Creek, AZ 85243
Phone
(480) 813-9191
(480) 813-0025 (Fax)
(480) 821-4715
(480) 813-0025 (Fax)
(480) 821-4715
Personal information
See more information about JAMES PARK COLEMAN at radaris.comName
Address
Phone
1037 Panicum Dr, Prescott, AZ 86305
2851 Smoke Tree Ln, Prescott, AZ 86301
Professional information
James P Coleman, Mesa AZ - PT (Physical therapy)
Specialties:
Physical Therapy
Address:
4566 E Inverness Ave SUITE 101, Mesa 85206
(480) 813-9191 (Phone), (480) 813-0025 (Fax)
(480) 813-9191 (Phone), (480) 813-0025 (Fax)
Languages:
English
James Park Coleman, Mesa AZ
Specialties:
Physical Therapist
Address:
4566 E Inverness Ave, Mesa, AZ 85206
Memories Utilizing Hybrid Error Correcting Code Techniques
US Patent:
2013026, Oct 3, 2013
Filed:
Dec 21, 2012
Appl. No.:
13/725298
Inventors:
JOSHUA D. RUGGIERO - Chandler AZ, US
James A. Coleman - Mesa AZ, US
Gary J. Lavelle - Newtown PA, US
James A. Coleman - Mesa AZ, US
Gary J. Lavelle - Newtown PA, US
International Classification:
G06F 11/10
US Classification:
714763
Abstract:
Use of hybrid error correcting code (ECC) techniques. A memory access request having an associated address is received. A memory controller determines whether the address corresponds to a first region of a memory for which ECC techniques are applied or a second region of the memory for which ECC techniques are not applied. The memory access is processed utilizing ECC techniques if the address corresponds to the first region of the memory, a transaction indicator and an execution unit indicator, and processed without utilizing the ECC techniques if the address corresponds to the second region of the memory.
Multi-Core Integrated Circuit Configurable To Provide Multiple Logical Domains
US Patent:
2014007, Mar 13, 2014
Filed:
Sep 13, 2012
Appl. No.:
13/615442
Inventors:
James A. Coleman - Mesa AZ, US
Durgesh Srivastava - Santa Clara CA, US
Gerald Rogers - Chandler AZ, US
Scott M. Oehrlein - Chandler AZ, US
Durgesh Srivastava - Santa Clara CA, US
Gerald Rogers - Chandler AZ, US
Scott M. Oehrlein - Chandler AZ, US
International Classification:
G06F 13/20
US Classification:
710316
Abstract:
Apparatuses, methods and storage media associated with integrated circuits (IC) or system-on-chips (SOC) are disclosed herein. In embodiments, a multi-core IC may include a number of central processing units (CPUs), and a number of input/output (I/O) resources. The IC may further include a switch fabric configured to couple the CPUs with the I/O resources, and a register to be selectively configured to exclusively couple one of the CPUs with one of the I/O resources to form a logical domain that computationally isolates the one CPU and the one I/O resource from other CPUs and other I/O. Other embodiments may be described and claimed.
Architecture And Method For Managing Interrupts In A Virtualized Environment
US Patent:
2014008, Mar 20, 2014
Filed:
Mar 29, 2012
Appl. No.:
13/976999
Inventors:
James A. Coleman - Mesa AZ, US
Scott M. Oehrlein - Chandler AZ, US
Scott M. Oehrlein - Chandler AZ, US
International Classification:
G06F 13/24, G06F 9/455
US Classification:
710260
Abstract:
A method may comprise identifying a signal indicating real-time mode operation for a guest operating system (OS) and directly routing an interrupt for a first processor to the guest OS while the guest OS is running without causing a transition from execution by the guest OS to execution by a host system. Other embodiments are disclosed and claimed.
Controlling A Processor Cache Using A Real-Time Attribute
US Patent:
2013025, Sep 26, 2013
Filed:
Dec 22, 2011
Appl. No.:
13/993052
Inventors:
James A. Coleman - Mesa AZ, US
Durgesh Srivastava - Cupertino CA, US
Durgesh Srivastava - Cupertino CA, US
International Classification:
G06F 12/12
US Classification:
711133
Abstract:
A processor device has a cache, and a cache controller that manages the replacement of a number of cache lines in the cache, in accordance with a replacement policy. A storage location is to be configured to define a memory map having a cacheable region, an un-cacheable region, and a real time region. Upon a cache miss of an address that lies in the real time region, the cache controller responds by loading content at the address into a cache line, and then prevents the cache line from aging as would a cache line that is in the cacheable region. Other embodiments are also described and claimed.