JAMES NICHOLAS WHOLEY
Pilots at Cyn Vw Dr, Saratoga, CA
License number
California A1066621
Issued Date
Jan 2016
Expiration Date
Jan 2018
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
21020 Canyon View Dr, Saratoga, CA 95070
Professional information
Low-Resistance, Fine-Line Semiconductor Device And The Method For Its Manufacture
US Patent:
4213840, Jul 22, 1980
Filed:
Nov 13, 1978
Appl. No.:
5/959792
Inventors:
Masahiro Omori - Palo Alto CA
James N. Wholey - Saratoga CA
J. Ross Anderson - Sunnyvale CA
James N. Wholey - Saratoga CA
J. Ross Anderson - Sunnyvale CA
Assignee:
Avantek, Inc. - Santa Clara CA
International Classification:
H01L 21441
US Classification:
204192C
Abstract:
A method of fabricating gate electrodes on microwave field effect transistors is described. A first layer of photo-resist is deposited and photolithographically defined on top of a semiconductor material with openings in the photoresist, corresponding to the gate electrode. In one embodiment, when drain and source electrodes have been previously formed, additional openings in the first layer of photoresist are defined that approximately overlay the drain and source electrodes. A metal layer is then deposited on top of this structure. A second layer of photoresist is then deposited and photolithographically defined on top of the first metal layer, with larger openings which overlay the openings in the first layer of photoresist. The thickness of the gate electrode, and in one embodiment, the sections overlaying the drain and source electrodes, is then increased by plating gold into the openings in the second layer of photoresist.
Amplifier System Having Compensated Amplification Variation
US Patent:
7292103, Nov 6, 2007
Filed:
Apr 14, 2005
Appl. No.:
11/107284
Inventors:
Chul Hong Park - San Jose CA, US
James Nicholas Wholey - Saratoga CA, US
James Nicholas Wholey - Saratoga CA, US
Assignee:
Avago Technologies Wireless IP (Singapore) Pte Ltd - Singapore
International Classification:
H03G 3/10, H03G 3/30
US Classification:
330280, 330129
Abstract:
An amplifier system is provided for amplifying an input signal to provide an amplified output signal, amplifying an amplified input signal to provide a further amplified output signal, and phase delay compensating variations of the amplifications of the amplified output signal and the further amplified output signal for providing the further amplified output signal with substantially linear amplification under a variable load.
Semiconductor Structure Comprising Pillar And Moisture Barrier
US Patent:
8344504, Jan 1, 2013
Filed:
Mar 30, 2011
Appl. No.:
13/075493
Inventors:
James Wholey - Saratoga CA, US
Ray Parkhurst - Santa Clara CA, US
Ray Parkhurst - Santa Clara CA, US
Assignee:
Avago Technologies Wireless IP (Singapore) Pte. Ltd. - Singapore
International Classification:
H01L 23/04, H01L 23/52
US Classification:
257730, 257776, 257E23068
Abstract:
A semiconductor structure includes multiple semiconductor devices on a substrate and a metal layer disposed over the semiconductor devices, the metal layer comprising at least a first trace and a second trace. A conductive pillar is disposed directly on and in electrical contact with the first trace of the metal layer, and a dielectric layer is selectively disposed between the metal layer and the conductive pillar, where the dielectric layer electrically isolates the second trace from the pillar. A moisture barrier surrounds the semiconductor devices around a periphery of the semiconductor structure, and extends from the substrate through the dielectric layer to the conductive pillar.
Semiconductor Structure Comprising Moisture Barrier And Conductive Redistribution Layer
US Patent:
8536707, Sep 17, 2013
Filed:
Nov 29, 2011
Appl. No.:
13/306708
Inventors:
James Wholey - Saratoga CA, US
Ray Myron Parkhurst - Santa Clara CA, US
Marshall Maple - Cupertino CA, US
Ray Myron Parkhurst - Santa Clara CA, US
Marshall Maple - Cupertino CA, US
Assignee:
Avago Technologies General IP (Singapore) Pte. Ltd. - Singapore
International Classification:
H01L 23/52
US Classification:
257758, 257760, 257774, 438627, 438643, 438653
Abstract:
A semiconductor structure includes semiconductor devices on a substrate, a moisture barrier on the substrate surrounding the semiconductor devices, and a metal conductive redistribution layer formed over the moisture barrier. The metal conductive redistribution layer and the moisture barrier define a closed compartment containing the semiconductor devices.
Low Voltage Bipolar Amplifier
US Patent:
5436595, Jul 25, 1995
Filed:
Aug 1, 1994
Appl. No.:
8/283877
Inventors:
James Wholey - Saratoga CA
Kevin Negus - Palo Alto CA
Kevin Negus - Palo Alto CA
Assignee:
Hewlett-Packard Company - Palo Alto CA
International Classification:
H03F 304
US Classification:
330296
Abstract:
A bipolar transistor amplifier with improved base biasing is disclosed. In the bias circuit of the present invention, the bias current only varies with the log(log) of variations in. beta. of the NPN transistors, making the circuit particularly resistant to temperature and process induced variations in. beta. A feedback loop also insures that the bias current will remain constant under normal operating conditions. In several embodiments of the present invention, the bias signal and the input signal are kept separate, reducing interference. The amplifier and bias circuit provides a large amount of voltage headroom even with low supply voltages.