JAMES N JOHNSTON
Electrician at Harpers Fry Ln, Austin, TX
License number
Texas 359645
Expiration Date
Feb 23, 2018
Category
Apprentice Electrician
Address
Address
3314 Harpers Ferry Ln, Austin, TX 78745
Phone
(737) 212-2538
Professional information
James W. Johnston, Austin TX - Lawyer
Address:
Board of Nurse Examiners For TX
333 460 STE 3, Austin 78701
(512) 305-6821
333 460 STE 3, Austin 78701
(512) 305-6821
Licenses:
Texas - Eligible To Practice In Texas 1987
Education:
St. Marys University School of LawDegree Doctor of Jurisprudence/Juris Doctor (J.D.)Graduated 1987
St. Marys University School of LawDegree Doctor of Jurisprudence/Juris Doctor (J.D.)Graduated 1987
St. Marys University School of LawDegree Doctor of Jurisprudence/Juris Doctor (J.D.)Graduated 1987
Specialties:
Administrative Law - 50%
Government - 50%
Government - 50%
Ceo/Owner At Johnston Construction Group
Position:
CEO/Owner at Johnston Construction Group
Location:
Austin, Texas Area
Industry:
Construction
Work:
Johnston Construction Group
since Aug 1970
-
CEO/Owner
Education:
The University of Texas at Austin 1967 - 1970
Howard College 1965 - 1966
A.A., Business
Howard College 1965 - 1966
A.A., Business
Multi-Chip Semiconductor Device And Method For Making The Device By Using Multiple Flip Chip Interfaces
US Patent:
6150724, Nov 21, 2000
Filed:
Mar 2, 1998
Appl. No.:
9/032860
Inventors:
James F. Wenzel - Austin TX
Robert K. DeHaven - Austin TX
Bryan D. Marietta - Austin TX
James P. Johnston - Austin TX
Robert K. DeHaven - Austin TX
Bryan D. Marietta - Austin TX
James P. Johnston - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H01L 2348, H01L 2352, H01L 2940
US Classification:
257777
Abstract:
A bump-bonded multi-chip flip-chip device (100) is formed by manufacturing a mother chip (102) having a first set (207) of bumps (212) and a second set (209) of bump contacts (210). A daughter chip (104) is also formed which has conductive bumps (312). The daughter chip (104) and the mother chip (102) are placed face-to-face and contact is made between the daughter chips bumps (312) and the mother chips bump contact regions (210). After interconnection of the daughter chip (104) and the mother chip (102), the mother chip (102) is contacted to an IC package (106) using the bumps (212). The package (106) uses a plurality of metallic layers interconnected selectively by conductive vias in order to route signals between the mother chip (102), the daughter chip (104), and external terminals (112) of the package (106).
Power Lead-On-Chip Ball Grid Array Package
US Patent:
8129226, Mar 6, 2012
Filed:
May 10, 2007
Appl. No.:
12/599625
Inventors:
James P. Johnston - Austin TX, US
Chu-Chung Lee - Round Rock TX, US
Tu-Anh N. Tran - Austin TX, US
James W. Miller - Austin TX, US
Kevin J. Hess - St. Ismier, FR
Chu-Chung Lee - Round Rock TX, US
Tu-Anh N. Tran - Austin TX, US
James W. Miller - Austin TX, US
Kevin J. Hess - St. Ismier, FR
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H01L 21/44
US Classification:
438123, 438106, 438124, 438127
Abstract:
A packaging assembly (), such as a ball grid array package, is formed which distributes power across an interior region of an integrated circuit die () by using an encapsulated patterned leadframe conductor () that is disposed over the die () and bonded to a plurality of bonding pads () formed in a BGA carrier substrate () and in the interior die region, thereby electrically coupling the interior die region to an externally provided reference voltage.