JAMES MILLER, R.PH.
Pharmacy at State St, Boise, ID

2003002, Jan 30, 2003

Sep 23, 2002

10/253844

Kurt Beigel - Boise ID, US
Manny Ma - Boise ID, US
Gordon Roberts - Meridian ID, US
James Miller - Boise ID, US
Daryl Habersetzer - Boise ID, US
Jeffrey Bruce - Meridian ID, US
Eric Stubbs - Boise ID, US

G11C007/00, G11C029/00

365/201000, 365/189110

As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

6028799, Feb 22, 2000

Mar 1, 1999

9/260232

Kurt D. Beigel - Boise ID
Manny K. Ma - Boise ID
Gordon D. Roberts - Meridian ID
James E. Miller - Boise ID
Daryl L. Habersetzer - Boise ID
Jeffrey D. Bruce - Meridian ID
Eric T. Stubbs - Boise ID

Micron Technology, Inc. - Boise ID

G11C 2900

365201

As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

6052322, Apr 18, 2000

Jul 28, 1999

9/363003

Kurt D. Beigel - Boise ID
Douglas J. Cutter - Boise ID
Manny K. Ma - Boise ID
Gordon D. Roberts - Meridian ID
James E. Miller - Boise ID
Daryl L. Habersetzer - Boise ID
Jeffrey D. Bruce - Meridian ID
Eric T. Stubbs - Boise ID

Micron Technology, Inc. - Boise ID

G11C 700

365201

As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

2002001, Feb 14, 2002

Dec 11, 2000

09/735157

Kurt Beigel - Boise ID, US
Manny Ma - Boise ID, US
Gordon Roberts - Meridian ID, US
James Miller - Boise ID, US
Daryl Habersetzer - Boise ID, US
Jeffrey Bruce - Meridian ID, US
Eric Stubbs - Boise ID, US

G11C007/00

365/201000, 365/200000, 365/205000, 365/207000, 365/203000, 365/189090, 714/718000

As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

5787096, Jul 28, 1998

Apr 23, 1996

8/636385

Gordon Roberts - Meridian ID
James E. Miller - Boise ID
Eric Stubbs - Boise ID

Micron Technology, Inc. - Boise ID

G11C 2900

371 211

A selector circuit (12) for placing a memory device (10) in test mode. The selector circuit (12) uses a logic circuit (26) to determine when a control signal provided to a pin of the memory device (10) maintains a first logic level for a period of time exceeding the specification for the control signal in normal operation. A multiplexer (24) receives the control signal and a substitute control signal at an alternate pin of the memory device. The substitute control signal is used in place of the control signal during the test. The output of the logic circuit (26) is coupled to control the multiplexer (24) to select the control signal for use in addressing a cell of the memory device (10) in normal operation and to select the substitute control signal for use in addressing a cell of the memory device (10) in test mode.

5679593, Oct 21, 1997

Feb 1, 1996

8/595232

James E. Miller - Boise ID
Manny K. F. Ma - Boise ID

Micron Technology, Inc. - Boise ID

H01L 21265

437 47

The present invention teaches fabrication of a high-resistance integrated circuit diffusion resistor that uses standard CMOS process steps. By appropriate masking during ion-implantation of source/drain diffusion regions, diffusion resistors created during NMOS source/drain implant may be counterdoped during PMOS source/drain implants and vice-versa. By appropriate choice of relative concentrations of a resistor dopant and counterdopant, and choice of diffusion depths, junction diodes can be formed which create a pinched resistor by constricting the current flow. The relative dopant concentrations can also be chosen to create regions of light effective doping within the diffusion resistor rather than creating junction diodes.

5677567, Oct 14, 1997

Jun 17, 1996

8/664409

Manny Kin F. Ma - Boise ID
Jeffrey D. Bruce - Boise ID
Daryl L. Habersetzer - Boise ID
Gordon D. Roberts - Meridian ID
James E. Miller - Boise ID

Micron Technology, Inc. - Boise ID

H01L 23495

257666

A device and method for increasing integrated circuit density comprising at least a pair of superimposed dice, wherein at least one of the superimposed dice has at least one bond pad variably positioned on an active surface of the die. A plurality of lead fingers from a leadframe extend between the dice. The leadframe comprises at least one lead with leads of non-uniform length and configuration to attach to the differently positioned bond pads of the multiple dice. An advantage of the present invention is that it allows dice with differing bond pad arrangements to be used in a superimposed configuration to increase circuit density, while eliminating the use of bond wires in such a configuration.

5990538, Nov 23, 1999

Nov 3, 1997

8/963103

James E. Miller - Boise ID
Manny K. F. Ma - Boise ID

Micron Technology, Inc. - Boise ID

H01L 298605

257536

The present invention teaches fabrication of a high-resistance integrated circuit diffusion resistor that uses standard CMOS process steps. By appropriate masking during ion-implantation of source/drain diffusion regions, diffusion resistors created during NMOS source/drain implant may be counterdoped during PMOS source/drain implants and vice-versa. By appropriate choice of relative concentrations of a resistor dopant and counterdopant, and choice of diffusion depths, junction diodes can be formed which create a pinched resistor by constricting the current flow. The relative dopant concentrations can also be chosen to create regions of light effective doping within the diffusion resistor rather than creating junction diodes.

6917230, Jul 12, 2005

Oct 17, 2003

10/688861

James E. Miller - Boise ID, US

Micron Technology, Inc. - Boise ID

H03L007/08

327158, 327156

Circuits and methods are provided that reduce, if not prevent, the adverse effects of transient noise on phase adjustments made by digital delay lock loop (DLL) circuits, which typically generate a periodic output signal having a particular phase relationship with a periodic input signal. A digital low pass filter of a DLL circuit includes circuitry, such as, for example, a thermometer register, coupled to receive the outputs of a DLL phase detector. The low pass filter prevents the DLL circuit from making frequent changes to the phase of the DLL output signal.