James Michael Shaffer
Engineering at 21 St, Boise, ID

7982662, Jul 19, 2011

Dec 8, 2009

12/633652

James Shaffer - Boise ID, US

Intellex, LLC - Eagle ID

G01S 7/02, G01S 7/48, G01S 13/00, G01S 17/00

342158, 702127, 702155, 702158, 702159, 342 27, 342 52, 342 53, 342 54, 342 59, 342 70, 342 73, 342 74, 342118, 342146, 342147, 342368, 244 31, 701300, 701301, 356 3, 356 401, 356 501, 250200, 2502011, 2502031, 2502032

This scanning array scans an area around the array for nearby objects, collision obstructions, and terrain topography. The scanning array can scan for sounds emitted by objects in the vicinity of the scanning array, passive energy receipt sources, or it can also send out an energy beam and scan for reflections from objects within the energy beam. The energy beam can be optical, laser, radar or other energy emitting sources. The scanning array of the invention can be used for helicopter detection and avoidance of collision risk and can be used for other scanning purposes. Scanning of an entire hemisphere or greater is accomplished by manipulating the scanner platform through the coordination of either linear actuators or gimbals so as to produce nutation without rotation. This motion allows transceivers to be directly coupled to transmitting and sensing modules without the losses associated with slip rings and other coupling devices.

5682064, Oct 28, 1997

Jan 23, 1995

8/611602

Glen G. Atkins - Boise ID
Michael S. Cohen - Boise ID
Karl H. Mauritz - Eagle ID
James M. Shaffer - Boise ID

Micron Technology, Inc. - Boise ID

H01L 23053, H01L 2312

257701

An apparatus for integrating wafer scale semiconductor integrated circuits and interfacing them with other systems. A wafer, partial wafer, die or plurality of same are mated to a printed circuit board (PCB) which electrically contacts the pads on each die using small conductive pillars. The PCB in turn is connected easily to other electronic systems. The entire apparatus is incorporated into other systems which utilize the dice in the apparatus. The apparatus may be fitted with heating elements and cooling channels to generate the necessary dice temperatures for burn-in, testing, and operation. The apparatus is easily adaptable to include more dice in a stacked configuration.

6081463, Jun 27, 2000

Feb 25, 1998

9/030498

James M. Shaffer - Boise ID
Brent Keeth - Boise ID
Eugene H. Cloud - Boise ID
Salman Akram - Boise ID

Micron Technology, Inc. - Boise ID

G11C 700

365200

Defective memory is programmed to have a contiguous address space by dividing the logical address space of the memory into a plurality of address sections. The address section containing the address mapped to a defective memory location is identified. The physical memory locations originally mapped to the addresses in the identified address section are remapped to addresses in an address section at one end of the address space. The addresses in the end address section are disabled. Alternatively, spare memory is provided and the addresses in the end address section are remapped to physical locations in the spare memory. A similar remapping procedure is applied to repair defective data paths in a memory. The remapping procedure is applicable to memory devices or memory modules.

5276834, Jan 4, 1994

Dec 4, 1990

7/621869

Karl H. Mauritz - Eagle ID
Thomas W. Voshell - Boise ID
James M. Shaffer - Boise ID

Micron Technology, Inc. - Boise ID

G06F 1216, G06F 1202

395425

A spare memory arrangement in which a defective chip in a memory array can be electronically replaced with a spare chip of identical construction. A defective memory chip is first detected and located by a suitable means, such as an error correction code (ECC), check sum, or parity check. A sparer chip is constructed to be actuated upon a read to the defective memory chip to replace the defective chip with a memory spare chip. The sparer chip includes a cross-point memory (CPM) cell having an address register for receiving data from a central processing unit (CPU) and routing the data to and from the spare memory chip. The cross-point memory (CPM) cell is actuated by control input from the (CPU).

5200917, Apr 6, 1993

Nov 27, 1991

7/800582

James M. Shaffer - Boise ID
Karl H. Mauritz - Boise ID
Glen Atkins - Boise ID

Micron Technology, Inc. - Boise ID

G11C 1300

365 51

The invention relates to a stacked integrated circuit module 20 which is interchangeable with standard printed circuit boards. Module 20 has two PCBs 22 and 24 and multiple memory ICs 26a-26d mounted on the PCBs. A board alignment support 48 is provided between PCBs 22 and 24 to support the PCBs in a spaced and substantially parallel relation and to provide electrical interfacing between the two PCBs. PCB 22 has an edge connector 44 adapted to be inserted into standard receptacle connectors provided on a mother board. According to this stacked arrangement, memory ICs 26c and 26d are addressable through connector 44, conductive paths formed on PCB 22, board alignment support 48, and conductive paths formed on PCB 24.

6131255, Oct 17, 2000

Aug 25, 1998

9/139452

Glen G. Atkins - Boise ID
Michael S. Cohen - Boise ID
Karl H. Mauritz - Eagle ID
James M. Shaffer - Boise ID

Micron Technology, Inc. - Boise ID

H01L 2168

29 2501

An apparatus for integrating wafer scale semiconductor integrated circuits and interfacing them with other systems. A wafer, partial wafer, die or plurality of same are mated to a printed circuit board (PCB) which electrically contacts the pads on each die using small conductive pillars. The PCB in turn is connected easily to other electronic systems. The entire apparatus is incorporated into other systems which utilize the dice in the apparatus. The apparatus may be fitted with heating elements and cooling channels to generate the necessary die temperatures for burn-in, testing, and operation. The apparatus is easily adaptable to include more dice in a stacked configuration.

5570032, Oct 29, 1996

Aug 17, 1993

8/108097

Glen G. Atkins - Boise ID
Michael S. Cohen - Boise ID
Karl H. Mauritz - Eagle ID
James M. Shaffer - Boise ID

Micron Technology, Inc. - Boise ID

G01R 106

324760

An apparatus for wafer scale burn-in and testing of semiconductor integrated circuits and a method for its utilization. A wafer is mated to a printed circuit board which electrically contacts the pads on each die using small conductive pillars. Single precise alignment of entire wafer within apparatus allows for testing all the dice on the wafer in parallel, eliminating need to probe each die individually. The apparatus is fitted with heating elements and cooling channels to generate the necessary wafer temperatures for burn-in and testing. The method of utilization eliminates processing of defective dice beyond burn-in and test, thereby increasing throughput.

5831445, Nov 3, 1998

Jun 7, 1996

8/661419

Glen G. Atkins - Boise ID
Michael S. Cohen - Boise ID
Karl H. Mauritz - Boise ID
James M. Shaffer - Boise ID

Micron Technology, Inc. - Boise ID

G01R 106

324760

An apparatus for wafer scale burn-in and testing of semiconductor integrated circuits and a method for its utilization is disclosed. A wafer is mated to a printed circuit board which electrically contacts the pads on each die using small conductive pillars. Single precise alignment of entire wafer within apparatus allows for testing all the dice on the wafer in parallel, eliminating need to probe each die individually. The apparatus is fitted with heating elements and cooling channels to generate the necessary wafer temperatures for burn-in and testing. The method of utilization eliminates processing of defective dice beyond burn-in and test, thereby increasing throughput.

5815427, Sep 29, 1998

Apr 2, 1997

8/825871

Eugene H. Cloud - Boise ID
Brent Keeth - Boise ID
Salman Akram - Boise ID
James M. Shaffer - Boise ID
Alex Closson - Boise ID

Micron Technology, Inc. - Boise ID

G11C 502, G11C 506, G11C 800

365 51

A modular circuit includes a memory module that has an array of memory cells, a communication module that has communication circuitry for coupling signals between the array and external circuitry, and an interconnection module that electrically interconnects the array on the memory module and the communication circuitry on the communication module. The memory and communication modules may also be mounted to the interconnection module. Alternatively, the memory and interface modules may be electrically interconnected and mounted to each other, in which case the interconnection module is not required.