MR. JAMES MERRIL ALLEN, M.M.F.T.
Social Work at Interstate Ave, Portland, OR
License number
Oregon OR T0104
Category
Social Work
Type
Addiction (Substance Use Disorder)
Address
Address
3550 N Interstate Ave, Portland, OR 97227
Phone
(503) 249-3434
(503) 254-6236
(503) 254-6236
Personal information
See more information about JAMES MERRIL ALLEN at radaris.comName
Address
Phone
14704 Rhine St, Portland, OR 97236
2447 Orchard Ave, Gresham, OR 97080
2385 Kathryn St, Hillsboro, OR 97124
2109 Greenwood Pl, Redmond, OR 97756
1804 29Th Ave, Portland, OR 97214
Professional information
Mechanical Engineer At Columbia Helicopters
Position:
Mechanical Engineer at Columbia Helicopters
Location:
Portland, Oregon
Industry:
Aviation & Aerospace
Work:
Columbia Helicopters
- Portland, OR since Jun 2012
-
Mechanical Engineer
Penn State University - Applied Research Lab
- Philadelphia, PA Jan 2008 - Jun 2012
-
Associate Research Engineer
Penn State University
- State College, Pennsylvania Area Dec 2005 - Dec 2007
-
Graduate Research Assistant
Volvo 3P - Chassis Design & Analysis Group
- Göteborg, Sweden May 2007 - Aug 2007
-
Engineering Intern
Center for Innovative Sintered Products
- State College, Pennsylvania Area May 2004 - Dec 2005
-
Engineering Intern
Education:
Penn State University 2005 - 2007
MS, Mechanical Engineering Penn State University 2001 - 2005
BS, Mechanical Engineering
MS, Mechanical Engineering Penn State University 2001 - 2005
BS, Mechanical Engineering
Owner, Visual Aid, Inc.
Position:
Executive Producer & Editor at Visual Aid, Inc.
Location:
Portland, Oregon Area
Industry:
Broadcast Media
Work:
Visual Aid, Inc.
- Portland, Oregon Area since Nov 2005
-
Executive Producer & Editor
Extreme Arts & Sciences
2003 - 2008
-
Freelance Editor
Fusion TV
Sep 2004 - Jul 2006
-
Senior Editor
ABC Sports
Sep 2002 - Jan 2005
-
College Football production
Cinema Journal
Sep 2001 - Jun 2003
-
Assistant Editor
Hewlett Packard
2000 - 2003
-
Producer
KBVR-TV
2000 - 2001
-
Station Manager
Education:
Oregon State University 1997 - 2001
BA, Film Studies
BA, Film Studies
Skills:
Video Production, Production, Editing, Final Cut Pro, Video Editing, Video, Videography, After Effects, Film, Motion Graphics, Avid, Post Production
James Allen - Tigard, OR
Work:
JA Logistics LLC
Transportation consultant MFP of Oregon - Lake Oswego, OR
Transportation Director Building Material transload - Portland, OR
Credit/Accounts Receivable Manager
Transportation consultant MFP of Oregon - Lake Oswego, OR
Transportation Director Building Material transload - Portland, OR
Credit/Accounts Receivable Manager
Education:
University of Oregon
BA in English Education
BA in English Education
None At None
Position:
None at None (Sole Proprietorship)
Location:
Portland, Oregon Area
Industry:
Computer Software
Work:
None
-
None
Determination Of Approaching Instruction Starvation Of Threads Based On A Plurality Of Conditions
US Patent:
6651158, Nov 18, 2003
Filed:
Jun 22, 2001
Appl. No.:
09/888274
Inventors:
David W. Burns - Portland OR
James D. Allen - Portland OR
Michael D. Upton - Portland OR
Darrell D. Boggs - Aloha OR
Alan B. Kyker - Davis CA
James D. Allen - Portland OR
Michael D. Upton - Portland OR
Darrell D. Boggs - Aloha OR
Alan B. Kyker - Davis CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 946
US Classification:
712205, 709103
Abstract:
In a multi-threaded processor, thread priority variables are set up in memory. According to an embodiment of the present invention, several conditions are monitored so as to determine an indication of instruction side starvation may be approaching. If such starvation is approaching, the starvation is resolved upon the expiration of a threshold counter or the like.
Processor Including Replay Queue To Break Livelocks
US Patent:
6785803, Aug 31, 2004
Filed:
Sep 22, 2000
Appl. No.:
09/667248
Inventors:
Amit A. Merchant - Portland OR
David J. Sager - Portland OR
James D. Allen - Portland OR
David J. Sager - Portland OR
James D. Allen - Portland OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 938
US Classification:
712219, 712244
Abstract:
A technique is provided for breaking a stalled condition or livelock in a processor having a replay queue. A livelock or stalled condition is detected. One or more instructions are temporarily stored in a replay queue. A release or break in the livelock or stalled condition is detected, and the instructions are then unloaded from the replay queue for replay or re-execution. For a multi-threaded processor, a stall is detected in one of the threads. Instructions of the stalled thread are temporarily stored in a replay queue, except the oldest instruction of the stalled thread which is allowed to replay or re-execute. This allows other threads to have access to execution and replay resources. Eventually, the oldest instruction will execute and retire, which breaks or releases the stalled thread. The instructions stored in the replay queue are then unloaded from the replay queue.
Determining Whether Thread Fetch Operation Will Be Blocked Due To Processing Of Another Thread
US Patent:
7010669, Mar 7, 2006
Filed:
Oct 10, 2003
Appl. No.:
10/682427
Inventors:
David W. Burns - Portland OR, US
James D. Allen - Portland OR, US
Michael D. Upton - Portland OR, US
Darrell D. Boggs - Aloha OR, US
Alan B. Kyker - Davis CA, US
James D. Allen - Portland OR, US
Michael D. Upton - Portland OR, US
Darrell D. Boggs - Aloha OR, US
Alan B. Kyker - Davis CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 9/50
US Classification:
712205, 712229, 718103, 718107
Abstract:
In a multi-threaded processor, thread priority variables are set up in memory. According to an embodiment of the present invention, several conditions are monitored so as to determine an indication of instruction side starvation may be approaching. If such starvation is approaching, the starvation is resolved upon the expiration of a threshold counter or the like.
Method And Apparatus For Assigning Thread Priority In A Processor Or The Like
US Patent:
7454600, Nov 18, 2008
Filed:
Jun 22, 2001
Appl. No.:
09/888273
Inventors:
David W. Burns - Portland OR, US
James D. Allen - Portland OR, US
Michael D. Upton - Portland OR, US
Darrell D. Boggs - Aloha OR, US
David J. Sager - Portland OR, US
James D. Allen - Portland OR, US
Michael D. Upton - Portland OR, US
Darrell D. Boggs - Aloha OR, US
David J. Sager - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 9/46
US Classification:
712219, 712228, 718103, 718108
Abstract:
In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.
Method And Apparatus For Assigning Thread Priority In A Processor Or The Like
US Patent:
7877583, Jan 25, 2011
Filed:
Nov 7, 2008
Appl. No.:
12/267394
Inventors:
David W. Burns - Portland OR, US
James D. Allen - Portland OR, US
Michael D. Upton - Portland OR, US
Darrell D. Boggs - Aloha OR, US
David J. Sager - Portland OR, US
James D. Allen - Portland OR, US
Michael D. Upton - Portland OR, US
Darrell D. Boggs - Aloha OR, US
David J. Sager - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 9/30
US Classification:
712228
Abstract:
In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.
Method And Apparatus For Assigning Thread Priority In A Processor Or The Like
US Patent:
2011023, Sep 29, 2011
Filed:
Jun 7, 2011
Appl. No.:
13/155055
Inventors:
David W. Burns - Portland OR, US
James D. Allen - Portland OR, US
Michael D. Upton - Portland OR, US
Darrell D. Boggs - Aloha OR, US
David J. Sager - Portland OR, US
James D. Allen - Portland OR, US
Michael D. Upton - Portland OR, US
Darrell D. Boggs - Aloha OR, US
David J. Sager - Portland OR, US
International Classification:
G06F 9/46
US Classification:
718103
Abstract:
In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.