JAMES MARVIN PICKETT
Pilots at Skyline Blvd, Portland, OR
License number
Oregon A2662152
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
10933 NW Skyline Blvd, Portland, OR 97231
Personal information
See more information about JAMES MARVIN PICKETT at radaris.comName
Address
Phone
4707 SW Campbell Ct #785, Portland, OR 97239
5345 SW Dover Ln, Portland, OR 97225
3914 Tommy Armour Ct, Redmond, OR 97756
420 2Nd St, Creswell, OR 97426
4707 Campbell St, Portland, OR 97239
Professional information
Very Large Scale Bipolar Integrated Circuit Process
US Patent:
4866001, Sep 12, 1989
Filed:
Jan 11, 1988
Appl. No.:
7/296899
Inventors:
James M. Pickett - Portland OR
Stanley C. Perino - Portland OR
Ralph E. Rose - Portland OR
Stanley C. Perino - Portland OR
Ralph E. Rose - Portland OR
Assignee:
Bipolar Integrated Technology, Inc. - Beaverton OR
International Classification:
H01L 21265
US Classification:
437 32
Abstract:
A bipolar VLSI process includes masking and patterning, implanting a P+ channel stop and locally oxidizing a lightly P-doped, monolithic silicon substrate to define a long, narrow collector region. An N-type collector is implanted in the collector region. The implants are diffused to form a shallow gradient P-N junction. Then, device features requiring a predetermined spacing and size are photolithographically defined along the length of the collector region. The device features and the collector region are made long enough for the features to readily transect the collector region even if the mask is misaligned. The active transistor and the collector, base and emitter contacts are self-aligned with the collector region so as to take advantage of the noncritical spacing of the preceding steps. A single polysilicon layer used to form base, collector and emitter contacts and a triple diffusion transistor. Portions of the substrate silicon and polysilicon are locally oxidized to isolate the contacts and to define emitter width.
Vlsi Triple-Diffused Polysilicon Bipolar Transistor Structure
US Patent:
5061982, Oct 29, 1991
Filed:
Jan 8, 1990
Appl. No.:
7/462104
Inventors:
Robert M. Drosd - Aloha OR
James M. Pickett - Portland OR
James M. Pickett - Portland OR
Assignee:
Bipolar Integrated Technology, Inc. - Beaverton OR
International Classification:
H01L 2702, H01L 2900, H01L 2972, H01L 2906
US Classification:
357 43
Abstract:
A bipolar VLSI process includes masking and patterning, implanting a P+ channel stop (32) and locally oxidizing a P-doped silicon substrate (21) to define a collector region, implanting an N-type collector (43) and diffusing the implants (40, 44). Device emitter, collector and base contact features (64, 66, 68) are photolithographically defined by two openings (54, 56) spaced lengthwise along the collector region. Low resistivity P- and N-type regions (74, 80) are implanted in the substrate in the openings and covered by local oxidation (86, 88). The collector region is preferably formed in a keyhole shape with a wide collector contact feature (66B) and adjoining region 80B and narrow base contact (68B) and emitter (64B) features and intervening region (74B). The substrate (22) is exposed in the emitter and contact features. A single polysilicon layer (94) is deposited, selectively doped and oxidized to form separate base, collector and emitter contacts (94) and a triple diffused NPN transistor (116, 92, 40).