James Lewis Wilson
Physician in Portland, OR
License number
Utah 180300-1205
Issued Date
Nov 18, 1988
Expiration Date
Dec 31, 1990
Category
Physician
Type
Physician & Surgeon
Address
Address
Portland, OR
Personal information
See more information about James Lewis Wilson at radaris.comName
Address
Phone
514 SE 18Th St, Troutdale, OR 97060
5139 SE 128Th Ave, Portland, OR 97236
Gresham, OR
Professional information
Independent Software Developer At Lifelong Health
Position:
Independent Software Developer at LifeLong Health
Location:
Portland, Oregon Area
Industry:
Health, Wellness and Fitness
Work:
LifeLong Health
since Mar 2012
-
Independent Software Developer
Wellsource Inc.
Dec 2007 - Feb 2012
-
VP Software Engeneering
Xerox Corporation
Jul 1987 - Feb 2001
-
Development Manager
Education:
Massachusetts Institute of Technology - Sloan School of Management 1999 - 2001
MS E&M, Engineering & Management University of California, Los Angeles 1980 - 1983
MS CS, Computer Science Loma Linda University 1978 - 1980
BS, Mathematics
MS E&M, Engineering & Management University of California, Los Angeles 1980 - 1983
MS CS, Computer Science Loma Linda University 1978 - 1980
BS, Mathematics
Independent Biotechnology Professional
Location:
Portland, Oregon Area
Industry:
Biotechnology
Work:
Clinimetrics
1989 - 2007
-
Chief Business Officer / Chief Operations Officer
Education:
University of Oregon 1979 - 1981
MS, Molecular Biology University of Oregon 1974 - 1978
Bachelor of Arts, Molecular Biology / Clinical Psychology
MS, Molecular Biology University of Oregon 1974 - 1978
Bachelor of Arts, Molecular Biology / Clinical Psychology
Owner, Garden Stories
Position:
Owner at Garden Stories
Location:
Portland, Oregon Area
Industry:
Architecture & Planning
Work:
Garden Stories
since Dec 2009
-
Owner
McMenamins
- Edgefield Nov 2010 - Mar 2012
-
Assistant Manager - Edgefield Gardens
Ceanothus Gardens
- San Francisco Sep 2005 - Apr 2010
-
Sole Proprietor
Education:
University of Oregon 1996 - 2000
Sr. Assoc. At Srg Partnership
Position:
Sr. Assoc. at SRG Partnership
Location:
Portland, Oregon Area
Industry:
Architecture & Planning
Work:
SRG Partnership
-
Sr. Assoc.
Transportation/Trucking/Railroad Professional
Location:
Portland, Oregon Area
Industry:
Transportation/Trucking/Railroad
Costumer Service At Jiffy Lube
Position:
Costumer service at Jiffy lube
Location:
Portland, Oregon Area
Industry:
Automotive
Work:
Jiffy lube
-
Costumer service
Method And Apparatus For Limiting Processor Clock Frequency
US Patent:
6633993, Oct 14, 2003
Filed:
Jan 22, 2002
Appl. No.:
10/051051
Inventors:
James A. Wilson - Portland OR
Robert F. Netting - Portland OR
Peter Des Rosier - Portland OR
Robert F. Netting - Portland OR
Peter Des Rosier - Portland OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 104
US Classification:
713501, 713601
Abstract:
A method and apparatus for limiting a processor clock frequency includes an overclocking prevention circuit. The overclocking prevention circuit includes a frequency limiting circuit having programmable fusible elements. The frequency limiting circuit outputs a signal identifying a maximum processor clock frequency based on the state of each of the fusible elements. A comparator circuit compares a selected processor clock frequency to the maximum processor clock frequency to determine if the selected processor clock frequency is permitted. If the selected processor clock frequency is not permitted, then the processor is not allowed to operate at the selected clock frequency.
Method And Apparatus For Limiting Processor Clock Frequency
US Patent:
6385735, May 7, 2002
Filed:
Dec 15, 1997
Appl. No.:
08/990526
Inventors:
James A. Wilson - Portland OR
Robert F. Netting - Portland OR
Peter Des Rosier - Portland OR
Robert F. Netting - Portland OR
Peter Des Rosier - Portland OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 104
US Classification:
713501, 713601
Abstract:
A method and apparatus for limiting a processor clock frequency includes an overclocking prevention circuit. The overclocking prevention circuit includes a frequency limiting circuit having programmable fusible elements. The frequency limiting circuit outputs a signal identifying a maximum processor clock frequency based on the state of each of the fusible elements. A comparator circuit compares a selected processor clock frequency to the maximum processor clock frequency to determine if the selected processor clock frequency is permitted. If the selected processor clock frequency is not permitted, then the processor is not allowed to operate at the selected clock frequency.
Computer Processor With Dynamic Setting Of Latency Values For Memory Access
US Patent:
6067606, May 23, 2000
Filed:
Dec 15, 1997
Appl. No.:
8/990525
Inventors:
Brian Holscher - Hillsboro OR
Jeffrey R. Jones - Aloha OR
James A. Wilson - Portland OR
Jeffrey R. Jones - Aloha OR
James A. Wilson - Portland OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 100, G06F 1200
US Classification:
711167
Abstract:
A computer processor includes a dynamic latency module. The dynamic latency module includes a read-only memory ("ROM") in which is stored a plurality of sets of latency values. The dynamic latency module further includes a register coupled to the ROM and adapted to store at least one set of the plurality of sets of latency values. The dynamic latency module dynamically sets a plurality of memory access latency values by determining an operating speed of the processor and implementing one of the plurality of sets of latency values based on the operating speed.
Method And Apparatus For Limiting Processor Clock Frequency
US Patent:
7395449, Jul 1, 2008
Filed:
Nov 6, 2006
Appl. No.:
11/593889
Inventors:
James A. Wilson - Portland OR, US
Robert F. Netting - Portland OR, US
Peter Des Rosier - Portland OR, US
Robert F. Netting - Portland OR, US
Peter Des Rosier - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1/04
US Classification:
713501, 713601
Abstract:
A method and apparatus for limiting a processor clock frequency includes an overclocking prevention circuit. The overclocking prevention circuit includes a frequency limiting circuit having programmable fusible elements. The frequency limiting circuit outputs a signal identifying a maximum processor clock frequency based on the state of each of the fusible elements. A comparator circuit compares a selected processor clock frequency to the maximum processor clock frequency to determine if the selected processor clock frequency is permitted. If the selected processor clock frequency is not permitted, then the processor is not allowed to operate at the selected clock frequency.