James Kent Naylor
Land Surveyors in West Kaysville, UT
License number
Utah 166837-9925
Issued Date
Oct 30, 1982
Expiration Date
Dec 31, 1999
Category
Engineer/Land Surveyor
Type
Engineer in Training - Obsolete
Address
Address
West Kaysville, UT
Professional information
Apparatuses, Systems And Methods For Applying Protective Coatings To Electronic Device Assemblies
US Patent:
2013025, Sep 26, 2013
Filed:
Mar 25, 2013
Appl. No.:
13/849790
Inventors:
Max Sorenson - Cottonwood Heights UT, US
James Kent Naylor - Kaysville UT, US
James Kent Naylor - Kaysville UT, US
Assignee:
HzO, Inc. - Draper UT
International Classification:
C23C 16/02
US Classification:
427 58, 118 72, 118719, 118715
Abstract:
A coating apparatus may be configured to concurrently receive and waterproof a large number of electronic device assemblies. The coating apparatus may include a track for transporting the electronic device assemblies into an application station. The application station may have a cubic shape, and include an entry door and an opposite exit door. The entry and exit doors may enable the introduction of substrates into the application station, as well as their removal from the application station. In addition, the entry and exit doors may enable isolation of the application station from an exterior environment and, thus, provide control over the conditions under which a moisture resistant material is applied to the substrates. Methods for making electronic devices and other substrates resistant to moisture are also disclosed.
Method Of Forming Low Resistance Gate For Power Mosfet Applications
US Patent:
8592277, Nov 26, 2013
Filed:
Sep 27, 2010
Appl. No.:
12/891147
Inventors:
Sreevatsa Sreekantham - Chandler AZ, US
Ihsiu Ho - Salt Lake City UT, US
Fred Session - Sandy UT, US
James Kent Naylor - Kaysville UT, US
Ihsiu Ho - Salt Lake City UT, US
Fred Session - Sandy UT, US
James Kent Naylor - Kaysville UT, US
Assignee:
Fairchild Semiconductor Corporation - South Portland ME
International Classification:
H01L 21/336
US Classification:
438270, 438589, 438664, 438677, 257E2141, 257E21199
Abstract:
A method for forming a trench gate field effect transistor includes forming, in a semiconductor region, a trench followed by forming a dielectric layer lining a sidewall and a bottom surface of the trench. The method also includes, forming a first polysilicon layer on the bottom surface of the trench. The method further includes, forming a conductive material layer on an exposed surface of the first polysilicon layer and forming a second polysilicon layer on an exposed surface of the conductive material layer. The method still further includes, performing rapid thermal processing to cause the first polysilicon layer, the second polysilicon layer and the conductive material layer to react.
Improved Method For Selectively Etching A Semiconductor Device
US Patent:
2001000, May 24, 2001
Filed:
May 14, 1999
Appl. No.:
09/312738
Inventors:
JAMES KENT NAYLOR - KAYSVILLE UT, US
International Classification:
H01L021/302
US Classification:
438/689000
Abstract:
According to an example embodiment, the present invention is directed to a method for manufacturing a semiconductor device. The device comprises a light-reflective layer and an anti-reflective coating layer over the light-reflective layer. A material is located over the anti-reflective coating layer. The semiconductor is selectively etched using a non-polymerizing oxygen-rich fluorocarbon chemistry. By using an oxygen-rich fluorocarbon chemistry, the use of a polymerizing etchant is eliminated, making the manufacture of such devices simpler.
Low Resistance Gate For Power Mosfet Applications And Method Of Manufacture
US Patent:
2007019, Aug 16, 2007
Filed:
Aug 29, 2006
Appl. No.:
11/467997
Inventors:
Sreevatsa Sreekantham - West Jordan UT, US
Ihsiu Ho - Salt Lake City UT, US
Fred Session - Sandy UT, US
James Kent Naylor - Kaysville UT, US
Ihsiu Ho - Salt Lake City UT, US
Fred Session - Sandy UT, US
James Kent Naylor - Kaysville UT, US
International Classification:
H01L 21/336, H01L 21/3205
US Classification:
438270, 438272, 438589
Abstract:
A trench gate field effect transistor is formed as follows. A trench is formed in a semiconductor region, followed by a dielectric layer lining sidewalls and bottom of the trench and extending over mesa regions adjacent the trench. A conductive seed layer is formed in a bottom portion of the trench over the dielectric layer. A low resistance material is grown over the conductive seed layer, wherein the low resistance material is selective to the conductive seed layer.
Reliable Wafer-Level Chip-Scale Package Solder Bump Structure In A Packaged Semiconductor Device
US Patent:
2008005, Mar 6, 2008
Filed:
Aug 30, 2007
Appl. No.:
11/847512
Inventors:
Dennis Lang - San Jose CA, US
Sonbol Vaziri - Salt Lake City UT, US
James Naylor - Kaysville UT, US
Eric Woolsey - Salt Lake City UT, US
Chung-Lin Wu - San Jose CA, US
Mike Gruenhagen - Salt Lake City UT, US
Neill Thornton - Corvallis OR, US
Sonbol Vaziri - Salt Lake City UT, US
James Naylor - Kaysville UT, US
Eric Woolsey - Salt Lake City UT, US
Chung-Lin Wu - San Jose CA, US
Mike Gruenhagen - Salt Lake City UT, US
Neill Thornton - Corvallis OR, US
International Classification:
H01L 23/48, H01L 21/00
US Classification:
257738000, 438113000, 257E23010
Abstract:
A wafer level chip scale package (WLCSP) includes a packaged semiconductor device with a plurality of solder bump pads, patterned passivation regions above each of the solder bump pads, a patterned under bump metallization (UBM) region on each of the solder bump pads and the passivation regions, a polyimide region over a portion of the UBM regions and the passivation regions, solder bumps formed on each of the UBM regions, and encapsulation material surrounding the semiconductor die except for at least a portion of each of the solder bumps.
Reliable Wafer-Level Chip-Scale Solder Bump Structure
US Patent:
2010011, May 13, 2010
Filed:
Jan 20, 2010
Appl. No.:
12/690179
Inventors:
Dennis Lang - San Jose CA, US
Sonbol Vaziri - Salt Lake City UT, US
James Kent Naylor - Kaysville UT, US
Eric Woolsey - Salt Lake City UT, US
Chung-Lin Wu - San Jose CA, US
Mike Gruenhagen - Salt Lake City UT, US
Neill Thornton - Corvallis OR, US
Sonbol Vaziri - Salt Lake City UT, US
James Kent Naylor - Kaysville UT, US
Eric Woolsey - Salt Lake City UT, US
Chung-Lin Wu - San Jose CA, US
Mike Gruenhagen - Salt Lake City UT, US
Neill Thornton - Corvallis OR, US
International Classification:
H01L 23/498
US Classification:
257738, 257E2307
Abstract:
A wafer level chip scale package (WLCSP) includes a semiconductor device with a plurality of solder bump pads, patterned passivation regions above each of the solder bump pads, a patterned under bump metallization (UBM) region on each of the solder bump pads and the passivation regions, a polyimide region over a portion of the UBM regions and the passivation regions, solder bumps formed on each of the UBM regions.
Apparatuses, Systems And Methods For Protecting Electronic Device Assemblies
US Patent:
2013028, Oct 31, 2013
Filed:
Jun 18, 2013
Appl. No.:
13/920804
Inventors:
Blake Stevens - Morristown NJ, US
Alan Rae - Wilson NY, US
Marc Kenneth Chason - Schaumburg IL, US
Dana Cox - American Fork UT, US
James Kent Naylor - Kaysville UT, US
Alan Rae - Wilson NY, US
Marc Kenneth Chason - Schaumburg IL, US
Dana Cox - American Fork UT, US
James Kent Naylor - Kaysville UT, US
International Classification:
C23C 16/02, C23C 16/04
US Classification:
36167901, 118719, 427 58, 427 8
Abstract:
An apparatus for applying a protective coating to a high volume of separate electronic device assemblies includes a treatment element that is configured to prepare the high volume of electronic devices before protective coatings are applied to the electronic devices. The apparatus also includes a coating element configured to apply protective coatings to the high volume of separate electronic device assemblies.