JAMES G CHAMBERS
Electrician at Province Ln, Dallas, TX
License number
Texas 10826
Expiration Date
Apr 8, 2017
Category
Journeyman Electrician
Address
Address
2119 Province Ln, Dallas, TX 75228
Phone
(469) 248-2756
Professional information
Multistage Deposition That Incorporates Nitrogen Via An Intermediate Step
US Patent:
6828200, Dec 7, 2004
Filed:
Jan 3, 2003
Appl. No.:
10/336441
Inventors:
James Joseph Chambers - Dallas TX
Mark Visokay - Richardson TX
Luigi Colombo - Dallas TX
Mark Visokay - Richardson TX
Luigi Colombo - Dallas TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 21336
US Classification:
438287, 438785, 438786, 257310, 257410, 257411
Abstract:
The present invention forms a nitrided dielectric layer without substantial harm to a semiconductor layer on which the dielectric layer is formed. The invention employs a multi-stage process in which dielectric sub-layers are individually nitrided before formation of a next dielectric sub-layer. The net result is a nitrided multi-layered dielectric layer comprised of a plurality of dielectric sub-layers wherein the sub-layers have been individually deposited and incorporated with nitrogen.
Senior Director, Foundry Engineering At Advanced Micro Devices
Position:
Senior Director, Foundry Engineering at Advanced Micro Devices
Location:
Dallas/Fort Worth Area
Industry:
Semiconductors
Work:
Advanced Micro Devices
since Nov 2010
-
Senior Director, Foundry Engineering
Texas Instruments
2000 - 2010
-
Manager, Front End Process Development, Advanced CMOS
Education:
North Carolina State University 1995 - 2000
Ph.D, Chemical Engineering, Semiconductor Processing and Physics
Ph.D, Chemical Engineering, Semiconductor Processing and Physics
James Chambers - Dallas, TX
Work:
P F CHANG'S CHINA BISTRO
MANAGER P F CHANG'S CHINA BISTRO - Dallas, TX
BARTENDER
MANAGER P F CHANG'S CHINA BISTRO - Dallas, TX
BARTENDER
Methods To Enhance Effective Work Function Of Mid-Gap Metal By Incorporating Oxygen And Hydrogen At A Low Thermal Budget
US Patent:
2011020, Aug 25, 2011
Filed:
May 4, 2011
Appl. No.:
13/100474
Inventors:
Hiroaki Niimi - Dallas TX, US
James Joseph Chambers - Dallas TX, US
James Joseph Chambers - Dallas TX, US
Assignee:
TEXAS INSTRUMENTS INCORPORATED - Dallas TX
International Classification:
H01L 21/28
US Classification:
438592, 257E21204
Abstract:
A process is disclosed of forming metal replacement gates for PMOS transistors with oxygen in the metal gates such that the PMOS gates have effective work functions above 4.85. Metal work function layers in the PMOS gates are oxidized at low temperature to increase their effective work functions to the desired PMOS range. Hydrogen may also be incorporated at an interface between the metal gates and underlying gate dielectrics. Materials for the metal work function layers and processes for the low temperature oxidation are disclosed.
Method Of Forming Mos Transistors Including Sion Gate Dielectric With Enhanced Nitrogen Concentration At Its Sidewalls
US Patent:
8450221, May 28, 2013
Filed:
Aug 4, 2010
Appl. No.:
12/850097
Inventors:
Brian K. Kirkpatrick - Allen TX, US
James Joseph Chambers - Dallas TX, US
James Joseph Chambers - Dallas TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 21/00
US Classification:
438786
Abstract:
A method of forming an integrated circuit (IC) having at least one MOS device includes forming a SiON gate dielectric layer on a silicon surface. A gate electrode layer is deposited on the SiON gate layer and then patterning forms a gate stack. Exposed gate dielectric sidewalls are revealed by the patterning. A supplemental silicon oxide layer is formed on the exposed SiON sidewalls followed by nitriding. After nitriding, a post nitridation annealing (PNA) forms an annealed N-enhanced SiON gate dielectric layer including N-enhanced SiON sidewalls, wherein along lines of constant thickness a N concentration at the N-enhanced SiON sidewalls is ≧ the N concentration in a bulk of the annealed N-enhanced SiON gate layer −2 atomic %. A source and drain region on opposing sides of the gate stack are formed to define a channel region under the gate stack.
Semiconductor Cmos Devices And Methods With Nmos High-K Dielectric Present In Core Region That Mitigate Damage To Dielectric Materials
US Patent:
7176076, Feb 13, 2007
Filed:
Apr 29, 2005
Appl. No.:
11/118843
Inventors:
James Joseph Chambers - Dallas TX, US
Mark Robert Visokay - Richardson TX, US
Luigi Colombo - Dallas TX, US
Mark Robert Visokay - Richardson TX, US
Luigi Colombo - Dallas TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 21/8238
US Classification:
438199, 257204, 438200
Abstract:
The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. An I/O dielectric layer is formed in core and I/O regions of a semiconductor device (). The I/O dielectric layer is removed () from the core region of the device. A core dielectric layer is formed in the core region (). A barrier layer is deposited and patterned to expose the NMOS devices of the core region (). The core dielectric layer is removed from the core NMOS devices (). A high-k dielectric layer is formed () over the core and I/O regions. Then, the high-k dielectric layer is removed () from PMOS regions/devices of the core region and the NMOS and PMOS regions/devices of the I/O region.
Use Of Indium To Define Work Function Of P-Type Doped Polysilicon
US Patent:
7026218, Apr 11, 2006
Filed:
Jun 10, 2004
Appl. No.:
10/865342
Inventors:
Antonio Luis Pacheco Rotondaro - Dallas TX, US
James J. Chambers - Dallas TX, US
Amitabh Jain - Allen TX, US
James J. Chambers - Dallas TX, US
Amitabh Jain - Allen TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 21/336
US Classification:
438283, 438217, 438301, 438302
Abstract:
The present invention pertains to formation of a PMOS transistor wherein a layer of silicon or SiGe inhibits p-type dopant from entering into an underlying gate dielectric layer. The p-type dopant can be added to a gate electrode material that overlies the silicon or SiGe layer and can diffuse down toward the silicon or SiGe layer. The layer of silicon or SiGe may be formed to a thickness of about 5 to 120 nanometers and doped with a dopant, such as indium (In), for example, to deter the p-type dopant from passing through the silicon or SiGe layer. The dopant may have a peak concentration within the layer of silicon or SiGe near the interface of the silicon or SiGe layer with the underlying layer of gate dielectric material. Allowing the gate electrode to be doped with the p-type dopant (e. g. , boron) facilitates forming the transistor with an associated work function having a desired value (e. g.
Semiconductor Cmos Devices And Methods With Nmos High-K Dielectric Formed Prior To Core Pmos Silicon Oxynitride Dielectric Formation Using Direct Nitridation Of Silicon
US Patent:
7351632, Apr 1, 2008
Filed:
Apr 29, 2005
Appl. No.:
11/118842
Inventors:
Mark Robert Visokay - Richardson TX, US
Luigi Colombo - Dallas TX, US
James Joseph Chambers - Dallas TX, US
Luigi Colombo - Dallas TX, US
James Joseph Chambers - Dallas TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 21/8238
US Classification:
438216, 438275, 438287, 257E21639
Abstract:
The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. An oxide layer is formed in core and I/O regions of a semiconductor device (). The oxide layer is removed () from the core region of the device. A high-k dielectric layer is formed () over the core and I/O regions. Then, the high-k dielectric layer is removed () from PMOS regions of the core and I/O regions. A silicon nitride layer is grown () within PMOS regions of the core and I/O regions by a low temperature thermal process. Subsequently, an oxidation process is performed () that oxidizes the silicon nitride into silicon oxynitride.
Low Temperature Poly Oxide Processes For High-K/Metal Gate Flow
US Patent:
2008024, Oct 9, 2008
Filed:
Apr 9, 2007
Appl. No.:
11/697993
Inventors:
Ajith Varghese - McKinnery TX, US
James J. Chambers - Dallas TX, US
James J. Chambers - Dallas TX, US
International Classification:
H01L 29/78, H01L 21/31
US Classification:
257410, 438788, 257E29255, 257E2124
Abstract:
An integrated circuit device is disclosed as comprising a feature that is susceptible to oxidation. A poly-oxide coating is used over the feature susceptible to oxidation to protect the feature susceptible to oxidation from oxidizing. Various method can be used to form the poly-oxide coating include conversion of a ploy-silicon coating using UV Olow temperature oxidation and plasma nitridation using either decoupled plasma nitridation or NHannealing.
Triple-Gate Mosfet Transistor And Methods For Fabricating The Same
US Patent:
2005018, Aug 25, 2005
Filed:
Apr 21, 2005
Appl. No.:
11/112463
Inventors:
James Chambers - Dallas TX, US
Mark Visokay - Richardson TX, US
Mark Visokay - Richardson TX, US
International Classification:
H01L021/336, H01L029/76
US Classification:
257288000, 438197000
Abstract:
Transistors and fabrication methods are presented in which a semiconductor body is deposited in a cavity of a temporary form structure above a semiconductor starting structure. The formed semiconductor body can be epitaxial silicon deposited in the form cavity over a silicon substrate, and includes three body portions, two of which are doped to form source/drains, and the other forming a transistor channel that overlies the starting structure. A gate structure is formed along one or more sides of the channel body portion to create a MOS transistor.