JAMES ELMER BARTLING
Pilots at Sean Dr, Chandler, AZ

2010025, Oct 14, 2010

Mar 29, 2010

12/748881

Stephen Bowling - Chandler AZ, US
James Bartling - Chandler AZ, US
Igor Wojewoda - Tempe AZ, US

H05B 41/36, H05B 41/24

315224, 315287

A fluorescent lamp light intensity dimming control generates a pulse width modulation (PWM) signal at about a fifty percent duty cycle and has very fine frequency change granularity to allow precise and smooth light dimming capabilities. Intermediate PWM signal frequencies between the frequencies that are normally generated from values in a period register of the PWM generator are provided with a variable frequency clock source to the PWM generator. Selection of each frequency from the plurality of frequencies available from the variable frequency clock source may be determined from a value stored in a variable frequency clock register. A microcontroller may be used to select appropriate frequencies for dimming control of the fluorescent lamp from the variable frequency clock source, and the period and duty cycle values used in generating the PWM signal at about a fifty percent duty cycle.

2006022, Oct 12, 2006

Feb 10, 2006

11/352026

James Bartling - Chandler AZ, US

H01L 23/02

257686000

Capture and monitoring of critical data from a microcontroller is performed without halting or changing normal program execution therein. Data is captured according to stored program addresses that may run in the background during operation of the microcontroller. When an address match occurs data may thereby be captured. The captured data may be output via an in-circuit debugger (ICD) interface to a workstation computer. Therefore, a program emulator is no longer necessary for program evaluation and debugging purposes.

2004015, Aug 5, 2004

Sep 20, 2001

09/957062

James Bartling - Chandler AZ, US

G06F003/00, G05B015/00

710/029000, 700/001000

A CAN module or a microcontroller comprises a CAN module which receives a serial bit stream. The CAN module comprises a filter register with a bit select input and a single bit output, a bit select unit for selecting a bit of the filter register in accordance with the serial bit stream, a comparator coupled with the single bit output and with the serial bit stream for generating a comparison signal, and a register receiving the comparison signal for accumulating a plurality of comparison results and for generating an acceptance signal.

7764213, Jul 27, 2010

Jul 1, 2008

12/165950

James E. Bartling - Chandler AZ, US
David L. Otten - Chandler AZ, US
D. C. Sessions - Phoenix AZ, US

Microchip Technology Incorporated - Chandler AZ

H03M 1/82

341152

A high resolution digital-to-analog converter comprises a programmable n-bit current digital-to-analog converter (IDAC), an m-bit programmable counter/timer, an integrator that converts the IDAC constant current charging a capacitor over time into an a precision (high resolution) analog voltage, and a sample and hold circuit for storing the precision analog voltage. The constant current from the IDAC is applied to the integrator for a time period determined by the programmable counter/timer, then the sample and hold circuit will sample the final voltage on the capacitor and store it as an analog voltage. The analog voltage resolution of this high resolution digital-to-analog converter is n+m bits or binary 2. In addition, a plurality of sample and hold circuits may be utilized for maintaining a plurality of analog output voltages.

2007005, Mar 1, 2007

Aug 31, 2005

11/215856

Roshan Samuel - Queen Creek AZ, US
James Bartling - Chandler AZ, US

G06F 17/10

708300000

A method of filtering one or more input signals, includes receiving one or more input signals, each having an input signal value. The method includes storing at least two instructions in a program memory to filter one or more of the input signals. Each instruction includes an opcode and identifies at least two input locations and at least one output location. The method includes, for one or more of the one or more input signals, and then for each instruction, fetching input values from the at least two input locations. The method further includes performing an operation on the input values to produce an output value, based on the opcode of the instruction and outputting the output value to at least one output location.

7979594, Jul 12, 2011

Jul 16, 2009

12/504268

James E. Bartling - Chandler AZ, US

Microchip Technology Incorporated - Chandler AZ

G06F 3/00

710 5

A CAN module or a microcontroller comprises a CAN module which receives a serial bit stream. The CAN module comprises a filter register with a bit select input and a single bit output, a bit select unit for selecting a bit of the filter register in accordance with the serial bit stream, a comparator coupled with the single bit output and with the serial bit stream for generating a comparison signal, and a register receiving the comparison signal for accumulating a plurality of comparison results and for generating an acceptance signal.

2008000, Jan 10, 2008

Sep 20, 2006

11/533421

James E. Bartling - Chandler AZ, US
Asif Iqbal - Bangalore, IN
Murugesan Raman - Bangalore, IN

G09G 3/36

345 87

A liquid crystal display (LCD) bias generator generates a plurality of bias voltages, e.g., four bias voltages, needed to drive a segmented LCD. The LCD bias generator has a voltage generator, e.g., charge pump, that may generate a most positive voltage, e.g., substantially equal to or more positive than V, on the integrated circuit that may also be used for maintaining proper reverse bias operation of well ties and analog switches of the integrated circuit. Other necessary LCD bias voltages, e.g., three voltages, may also be derived from the LCD bias generator to provide bias and contrast control voltages required by the LCD. Having a more positive bias voltage than the power supply voltage, V, allows Vto cover a wider range of voltages, e.g., powered from a battery, by eliminating the need for complex analog switch and pad designs for the integrated circuit.

8217664, Jul 10, 2012

Apr 4, 2011

13/079093

James E. Bartling - Chandler AZ, US

Microchip Technology Incorporated - Chandler AZ

G01R 27/26, G01R 31/08, G01R 19/00, G04F 1/00

324658, 324535, 324 7611, 368 89

A time period of an event is determined by charging a known value capacitor from a constant current source during the event. The resultant voltage on the capacitor is proportional to the event time period and may be calculated from the resultant voltage and known capacitance value. Capacitance is measured by charging a capacitor from a constant current source during a known time period. The resultant voltage on the capacitor is proportional to the capacitance thereof and may be calculated from the resultant voltage and known time period. A long time period event may be measured by charging a first capacitor at the start of the event and a second capacitor at the end of the event, while counting clock times there between. Delay of an event is done by charging voltages on first and second capacitors at beginning and end of event, while comparing voltages thereon with a reference voltage.

8022714, Sep 20, 2011

May 6, 2008

12/115672

James E. Bartling - Chandler AZ, US

Microchip Technology Incorporated - Chandler AZ

G01R 27/26

324658, 324686, 324678

Capacitance is measured by charging a capacitor from a constant current source during a known time period. The resultant voltage on the capacitor is proportional to the capacitance thereof and may be calculated from the resultant voltage and known time period.

2014004, Feb 6, 2014

Jan 29, 2013

13/753341

Microchip Technology Incorporated - , US
James Bartling - Chandler AZ, US

Microchip Technology Incorporated - Chandler AZ

G06F 1/06

713600

A microcontroller has a programmable timebase, wherein the timebase has a trigger input to start a timer or counter of the timebase and wherein the timebase can be configured to operate upon receiving a trigger signal in a first mode to generate a plurality of timer/counter event signals until a reset bit in a control register is set and in a second mode to generate a single timer/counter event signal and wherein the timebase can be configured to operate in a third mode to generate a predefined number of timer/counter event signals, wherein the predefined number is defined by a plurality of bits of a register.