JAMES EDWARD ANDERSON, JR
Pilots at Pioneer Dr, Huntington Beach, CA
License number
California A5083706
Issued Date
Aug 2013
Expiration Date
Aug 2018
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
9032 Pioneer Dr, Huntington Beach, CA 92646
Professional information
James Anderson - Huntington Beach, CA
Work:
UTC Aerospace
787 Thrust Reverser R&D Assembly Fab Mechanic The Boeing Company - Mesa, AZ
AH-64D Apache Assembly Structures Mechanic Lockheed Martin Corporation - Fort Worth, TX
F-35 Structures Mechanic / Final Assembly Inspector Northrop Grumman Corporation - Palmdale, CA
F-35 Structures Mechanic / Final Assembly Inspector Gulfstream Aerospace - Long Beach, CA
Senior Sheetmetal Technician XpressPrint - Huntington Beach, CA
Business Owner / Operations Manager Northrop Grumman Technical Services - Palmdale, CA
Field Service Technician / Life Cycle Support & Revitalization XpressPrint - Santa Clarita, CA
Business Owner / Operations Manager Signs By Tomorrow - Santa Clarita, CA
Operations Manager and Trainer 24 Hour Fitness - Canyon Country, CA
Certified Personal Trainer U.S. Air Force - Edwards AFB, CA
Supervisor and Aircraft Structures Mechanic Craftsman United State Air Force - Seymour-Johnson AFB, NC
Aircraft Structures Mechanic Journeyman
787 Thrust Reverser R&D Assembly Fab Mechanic The Boeing Company - Mesa, AZ
AH-64D Apache Assembly Structures Mechanic Lockheed Martin Corporation - Fort Worth, TX
F-35 Structures Mechanic / Final Assembly Inspector Northrop Grumman Corporation - Palmdale, CA
F-35 Structures Mechanic / Final Assembly Inspector Gulfstream Aerospace - Long Beach, CA
Senior Sheetmetal Technician XpressPrint - Huntington Beach, CA
Business Owner / Operations Manager Northrop Grumman Technical Services - Palmdale, CA
Field Service Technician / Life Cycle Support & Revitalization XpressPrint - Santa Clarita, CA
Business Owner / Operations Manager Signs By Tomorrow - Santa Clarita, CA
Operations Manager and Trainer 24 Hour Fitness - Canyon Country, CA
Certified Personal Trainer U.S. Air Force - Edwards AFB, CA
Supervisor and Aircraft Structures Mechanic Craftsman United State Air Force - Seymour-Johnson AFB, NC
Aircraft Structures Mechanic Journeyman
Education:
Orange Coast College - Costa Mesa, CA
Associates of Science in Engineering (Pending) Hamilton High School - Hamilton, OH
Associates of Science in Engineering (Pending) Hamilton High School - Hamilton, OH
Military:
Rank: SSgt / E-5L.i.location.original
Skills:
Supervisory: Natural leadership ability, training and evaluation of personnel, training program development, perform and write performance reviews and promotional recommendations, counsel personnel, ensure safety compliance and oversee incident investigations, familiarization with AS9100 and military specifications and experience interfacing with customer source representatives, government sources, internal departments and senior management. Mechanic: Vast experience in structures, composites and aerospace maintenance, materials and processes, superior quality of work, time management, team player, damage assessment and reporting, parts fabrication and repair, and process improvement. Inspector: Quality assurance, First Article Inspection and final assembly inspection experience, root cause analysis and corrective action, detail oriented and familiarization with lean manufacturing processes. Additional: Operation of ground support equipment, forklifts, overhead cranes and hydraulic carts, operational and production certifications from Boeing, Lockheed Martin, Northrop Grumman and UTC Aerospace, well versed in Microsoft Office applications and PC and MAC computer systems. Languages: English, Italian, Spanish, Serbian and Croatian
Extended Play Radio Vision Cassette Recorder System And Method Of Operating Same
US Patent:
6249642, Jun 19, 2001
Filed:
May 28, 1997
Appl. No.:
8/864637
Inventors:
Richard A. Lewis - El Segundo CA
James M. Anderson - Huntington Beach CA
James M. Anderson - Huntington Beach CA
Assignee:
TRW Inc. - Redondo Beach CA
International Classification:
H04N 591
US Classification:
386 96
Abstract:
An extended play radio video cassette recorder (EPRVCR) capable of receiving and recording audio and video signals transmitted over a radio frequency channel is provided. The EPRVCR includes a videocassette recorder (VCR) and a tuner capable of receiving of radio frequency signals and television frequency signals electrically connected to the VCR. Method for broadcasting and receiving a composite video and audio signal over a radio frequency for subsequent recording by an extended play radio video cassette recorder is also provided. The method includes the steps of providing a VCR having a tuner capable of receiving radio frequency signals; broadcasting audio on a preselected baseband radio frequency; broadcasting a visual image on a subcarrier sideband of the preselected baseband frequency; and receiving the audio and visual image using the tuner of the VCR. The VCR is also capable of recording the audio and video image simultaneously onto a single video cassette. The EPRVCR is also capable of playing the audio and visual image through the VCR for display on a monitor.
Method Of Making An Adaptive Configurable Gate Array
US Patent:
5217916, Jun 8, 1993
Filed:
Feb 4, 1991
Appl. No.:
7/651068
Inventors:
James M. Anderson - Huntington Beach CA
Andrew R. Coulson - Santa Monica CA
Vincent J. Demaioribus - Redondo Beach CA
Henry T. Nicholas - Redondo Beach CA
Andrew R. Coulson - Santa Monica CA
Vincent J. Demaioribus - Redondo Beach CA
Henry T. Nicholas - Redondo Beach CA
Assignee:
TRW Inc. - Redondo Beach CA
International Classification:
H01L 2180, H01L 21304
US Classification:
437 51
Abstract:
A new configurable gate array is defined in a master slice wafer form without borders of the kind currently known between constituent transistor gates, effectively providing a sea of gates over the wafer, interrupted if at all by islands, containing markers or the like; and a resultant application specific integrated circuit formed of such master slice is defined. In the IC, transistor gate cells, which are the same type of cells used for other purposes in the IC, are configured to serve the input and output function. Accordingly, the input and output function may be placed on any location in the IC. As an incident to personalization of the wafer saw lanes are formed of channels that extend over transistor cells and the latter cells are consequently destroyed in slicing the wafer. Means are also disclosed for an improved E-beam lithographic apparatus which permits an IC chip to be placed on an area of a wafer that is occupied by a marker, providing a wiring or macro design that avoids the marker.
Chip-To-Board Connection Assembly And Method Therefor
US Patent:
6219254, Apr 17, 2001
Filed:
Apr 5, 1999
Appl. No.:
9/286282
Inventors:
Gershon Akerling - Culver City CA
James M. Anderson - Huntington Beach CA
John W. Spargo - Redondo Beach CA
Benjamin Tang - Hawthorne CA
James M. Anderson - Huntington Beach CA
John W. Spargo - Redondo Beach CA
Benjamin Tang - Hawthorne CA
Assignee:
TRW Inc. - Redondo Beach CA
International Classification:
H05K 118
US Classification:
361763
Abstract:
The chip-to-board (or chip-to-MCM) connection assembly and method therefor features a semiconductor chip (31) having a front surface (31f) on which external terminal pads are provided; a board or MCM (32) having a surface (e. g. , a recessed surface) at a first side thereof to which the rear surface (31r) of the chip is affixed; and a connection carrier (33), disposed as an overlay, which electrically links the chip and the board or MCM. In this assembly scheme, the connection carrier (e. g. , a bump carrier) which is affixed to both the chip and the board or MCM, contains all required signal line tracings (57) to provide the electrical interconnection between the semiconductor chip and the board or MCM. The bump carrier replaces all bond wires (24) and the like and can include support/control circuitry, passive and/or active, associated with, for example, high-speed/high-power IC chips (51). The connection carrier (33) is provided with the electrical contacts (34) such as bump electrodes each interconnecting a contact location (37) at the surface side of the connection carrier facing the semiconductor chip and the oppositely disposed (i) external pad on the chip or (ii) external pad or landing (35) at a side of the board (32) facing the connection carrier (33).
Configurable Amplifier Array Incorporating Programmable Ehf Transmission Lines
US Patent:
7032189, Apr 18, 2006
Filed:
Oct 31, 2002
Appl. No.:
10/285150
Inventors:
Eric L. Upton - Bellevue WA, US
James M. Anderson - Huntington Beach CA, US
James M. Anderson - Huntington Beach CA, US
Assignee:
Northrop Grumman Corporation - Los Angeles CA
International Classification:
G06F 17/50
US Classification:
716 1, 716 7, 716 10, 716 15
Abstract:
A configurable circuit array that includes a matrix of cells, where each cell includes interconnected analog and/or digital circuit elements. The cells are fabricated on a common semiconductor substrate, and are electrically isolated from each other. The circuit elements in the cells are electrically coupled to circuit elements in other cells, and are electrically coupled to bonding pads by coaxial transmission lines capable of transmitting extremely high frequency signals. The transmission lines include a center conductor and first and second shield conductors, where the shield conductors prevent cross-talk interference. The transmission lines extend vertically from the substrate until they are a suitable distances above the circuit elements in the cell. From there, the transmission lines extend horizontally relative to the substrate to the opposite end connection point, where they again extend vertically down to the substrate.
High Performance Vias For Vertical Ic Packaging
US Patent:
6936913, Aug 30, 2005
Filed:
Dec 11, 2002
Appl. No.:
10/317680
Inventors:
Gershon Akerling - Culver City CA, US
James M. Anderson - Huntington Beach CA, US
Eric L. Upton - Bellevue WA, US
James M. Anderson - Huntington Beach CA, US
Eric L. Upton - Bellevue WA, US
Assignee:
Northrop Grumman Corporation - Los Angeles CA
International Classification:
H01L023/02
US Classification:
257686, 257687, 257688, 257689, 438109
Abstract:
A semiconductor device, a microelectromechanical system package and a method of making the same utilize high performance vias for vertical IC packaging. A semiconductor die of the device/package has a substrate with integrated circuitry formed on a front side of the substrate. A metal bonding pad overlies the substrate on the front side of the substrate and is electrically connected to the integrated circuitry. A solder bump is located on the metal bonding pad. An electrically conductive via extends through the substrate from the metal bonding pad to a back side of the substrate where the via forms a side wall of a via hole. A plurality of the substrates are stacked on one another with the outer end of the solder bump of one substrate fitting within the via hole of an adjacent substrate. During reflow soldering, surface tension forces of the molten solder bump self-align the substrates.
Burst Communications Apparatus And Method Using Tapped Delay Lines
US Patent:
7369600, May 6, 2008
Filed:
Dec 22, 2003
Appl. No.:
10/740766
Inventors:
Eric L. Upton - Belleview WA, US
James M. Anderson - Huntington Beach CA, US
Edward M. Garber - Los Angeles CA, US
James M. Anderson - Huntington Beach CA, US
Edward M. Garber - Los Angeles CA, US
Assignee:
Northrop Grumman Corporation - Los Angeles CA
International Classification:
H04B 1/00
US Classification:
375142, 324 7633, 324 7635, 324 7654, 331 57, 359306, 359331, 375365, 375366, 375367, 375373, 375376
Abstract:
A communications apparatus and method use tapped delay lines as multiplexers and demultiplexers. In one embodiment, a receiver () uses a tapped delay line () as a demultiplexer to acquire a burst communication at very high data rates in the range of 2. 5 to 80 Gbps with low preamble overhead. A sliding window correlator () continually samples the delay line () to determine when a PN encoded word is contained therein. The transmission frequency is pre-acquired before any data is present through the use of a ring oscillator frequency calibration loop () that is imbedded within the tapped delay line ().
Cross-Point Switch With Equalized Inputs
US Patent:
2004008, Apr 29, 2004
Filed:
Oct 23, 2002
Appl. No.:
10/278544
Inventors:
Benjamim Tang - Rancho Palos Verdes CA, US
James Anderson - Huntington Beach CA, US
James Anderson - Huntington Beach CA, US
International Classification:
H04L012/50
US Classification:
370/370000
Abstract:
A cross-point switch includes at least one signal input port and a signal equalizer connected to the signal input port. The signal equalizer compensates for low pass attenuation effects on an input signal present at the signal input port. The cross-point switch also includes a switch fabric connected to the signal equalizer, and at least one switch output port coupled to the switch fabric. An address controller and switch fabric control bus may be used to control the mapping of input ports to output ports. Each input port may optionally be connected to a set of signal equalizers. A multiplexer may be connected to each of the signal equalizers for connecting one signal equalizer output through a multiplexer output to the switch fabric.
On Chip Current Limiter
US Patent:
5386336, Jan 31, 1995
Filed:
Jun 19, 1992
Appl. No.:
7/901469
Inventors:
Jason S.-M. Kim - Los Angeles CA
James M. Anderson - Huntington Beach CA
James M. Anderson - Huntington Beach CA
Assignee:
TRW Inc. - Redondo Beach CA
International Classification:
H03K 1712
US Classification:
361 93
Abstract:
A current limiting circuit and technique is provided for preventing excessive current supplied to a circuit and for providing self-recovery characteristics thereto. The current limiting circuit includes an input for receiving a supply voltage for supplying power to the monitored circuit and an output for providing the power to the desired circuit being monitored. The circuit employs a drive transistor having a source connected to the input and a drain connected to the output. The drive transistor further includes a gate for receiving a control signal. A current mirror circuit is provided for sensing a current overload and adjusting the control signal to indicate the amount of current drawn. During normal current draw, the circuit provides the supply voltage as the output. When excessive current draw is detected, the drive transistor is turned off and the output current is thereby cut off.
Method For Packaging Integrated Circuit Chips
US Patent:
7135779, Nov 14, 2006
Filed:
Apr 14, 2004
Appl. No.:
10/823877
Inventors:
James Anderson - Huntington Beach CA, US
Gershon Akerling - Culver City CA, US
Gershon Akerling - Culver City CA, US
Assignee:
Northrop Grumman Corporation - Los Angeles CA
International Classification:
H01L 23/48
US Classification:
257778, 257774, 257E23011
Abstract:
A method for packaging integrated circuits in a wafer format that eliminates wire bonds. A wafer substrate on which the integrated circuits have been fabricated is patterned and etched to form signal and ground via through the substrate. A back-side ground plane is deposited in contact with the ground vias. A protective layer is formed on the top surface of the substrate, and a protective layer is formed on the bottom surface of the substrate, where the bottom protective layer fills in removed substrate material between the integrated circuits. Vias are formed through the bottom protective layer, and the wafer substrate is diced between the integrated circuits.