Position:
Contract ASIC Verification Engineer - Intel at Protingent
Location:
Greater Minneapolis-St. Paul Area
Work:
Protingent
- Irvine, CA since Dec 2012
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Contract ASIC Verification Engineer - Intel
LanceSoft Inc
- Greater Boston Area Mar 2012 - Sep 2012
-
Contract DFT Verification Engineer - AMD
CTG
- Rochester, Minnesota Area Oct 2009 - Jul 2011
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Digital Design Engineering Professional
Computer Task Group
Jul 2008 - Jul 2009
-
H/W Engineer on contract with IBM
Unisys
Oct 2001 - Dec 2007
-
Senior Hardware Engineer
Education:
Navy Technical training center
Honor & Awards:
Some US Patent co-invention awards, eight total, 1 pending
US Patent 6,993,630 - Data pre-fetch system and method for a cache memory
US Patent 6,973,541 - System and method for initializing memory within a data processing system
US Patent 6,976,128 - Cache flush system and method
US Patent 7,096,322 - Instruction processor write buffer emulation using embedded emulation control instructions