JAMES DAVID DUNDAS
Pilots at Weatherwood Cv, Austin, TX
License number
Texas C1008211
Category
Airmen
Address
Address
6405 Weatherwood Cv, Austin, TX 78746
Professional information
Branch Predictor Accuracy By Forwarding Table Updates To Pending Branch Predictions
US Patent:
2012012, May 17, 2012
Filed:
Nov 16, 2010
Appl. No.:
12/947206
Inventors:
JAMES David DUNDAS - Austin TX, US
Nikhil Gupta - Sunnyvale CA, US
Marvin Denman - Round Rock TX, US
Nikhil Gupta - Sunnyvale CA, US
Marvin Denman - Round Rock TX, US
International Classification:
G06F 9/38
US Classification:
712240, 712E09045
Abstract:
A method and apparatus are provided for increasing the accuracy of a branch predictor. A branch prediction table provides a first instance of a branch prediction value associated with an instruction being speculatively executed a first time; and provides a second instance of the branch prediction value associated with the instruction being speculatively executed a second rime. The first instance of the branch prediction value may be subsequently revised after the instruction associated with the first instance of the branch prediction value is retired. Information regarding whether that branch instruction was accurately predicted may then be used to update the branch prediction table and the second instance of the branch prediction value.
Repair Of Mis-Predicted Load Values
US Patent:
2003017, Sep 11, 2003
Filed:
Mar 6, 2002
Appl. No.:
10/091825
Inventors:
James Dundas - Austin TX, US
International Classification:
G06F009/00
US Classification:
712/225000
Abstract:
When fetching a load value for a load instruction results in a cache miss, the load instruction and any load-dependent instructions may be speculatively executed with a predicted load value and retired before the missing cache line is retrieved and the actual load value is determined. By storing the predicted load value in a table, when the actual load value is determined it may be compared with the predicted load value from the table. If the predicted load value was incorrect, the load and load-dependent instructions may be re-executed with the actual load value. A compiler may determine which load instructions are highly predictable and likely to result in cache misses, and designate only those load instructions for speculative execution.
Controlling A Memory Array
US Patent:
2014005, Feb 27, 2014
Filed:
Aug 23, 2012
Appl. No.:
13/593343
Inventors:
James D. Dundas - Austin TX, US
Assignee:
ADVANCED MICRO DEVICES, INC. - Sunnyvale CA
International Classification:
G06F 12/00
US Classification:
711104, 711147, 711E12001
Abstract:
Methods and systems for controlling a memory array are provided. A method of controlling a memory array includes: providing a next index to be read that indicates a location in the memory array from which to retrieve an output; reading validity information from a validity memory unit; comparing the next index with a last read index stored in an index memory unit; reading the output from an output memory unit when the last read index is the same as the next index and the validity information indicates the output in the output memory unit is valid; and reducing power to the memory array when the output is read from the output memory unit.
Hybrid Branch Prediction Device With Sparse And Dense Prediction Caches
US Patent:
8181005, May 15, 2012
Filed:
Sep 5, 2008
Appl. No.:
12/205429
Inventors:
James D. Dundas - Austin TX, US
Anthony X. Jarvis - Acton MA, US
Anthony X. Jarvis - Acton MA, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 9/32, G06F 9/38
US Classification:
712239, 712240
Abstract:
A system and method for branch prediction in a microprocessor. A hybrid device stores branch prediction information in a sparse cache for no more than a common smaller number of branches within each entry of the instruction cache. For the less common case wherein an i-cache line comprises additional branches, the device stores the corresponding branch prediction information in a dense cache. Each entry of the sparse cache stores a bit vector indicating whether or not a corresponding instruction cache line includes additional branch instructions. This indication may also be used to select an entry in the dense cache for storage. A second sparse cache stores entire evicted entries from the first sparse cache.
Power Efficient Pattern History Table Fetch In Branch Predictor
US Patent:
2012012, May 17, 2012
Filed:
Nov 16, 2010
Appl. No.:
12/947401
Inventors:
Anthony Jarvis - Acton MA, US
James David Dundas - Austin TX, US
James David Dundas - Austin TX, US
Assignee:
ADVANCED MICRO DEVICES, INC. - Sunnyvale CA
International Classification:
G06F 9/38
US Classification:
712240, 712E09045
Abstract:
A method and apparatus for branch prediction is disclosed. A pattern history table (PHT) is accessed based on at least one global history value to obtain a prediction value. The prediction value and the at least one global history value used to obtain the prediction value are placed in a queue. If a branch prediction is requested, the queue is accessed to obtain a prediction value. The queue may include any number of entries and the queue maintains the oldest prediction value at the head of the queue. The prediction value at the head of the queue is used when a branch prediction is needed.
Method And Apparatus For Satisfying Load Operations
US Patent:
7062617, Jun 13, 2006
Filed:
Mar 26, 2002
Appl. No.:
10/108061
Inventors:
James David Dundas - Austin TX, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 12/00
US Classification:
711154, 711169
Abstract:
A method and apparatus for satisfying load operations by accessing data from a store buffer is described herein. It is a further goal of the present invention to satisfy load operations faster than prior art techniques in most cases. Finally, it is a goal of the present invention to provide an improved technique for satisfying load operations that does not significantly impact processor performance in the event that a present load is not satisfied within a predetermined amount of time.
Branch Prediction Scheme Utilizing Partial-Sized Targets
US Patent:
2012012, May 17, 2012
Filed:
Nov 12, 2010
Appl. No.:
12/945732
Inventors:
James D. Dundas - Austin TX, US
Marvin A. Denman - Round Rock TX, US
Marvin A. Denman - Round Rock TX, US
International Classification:
G06F 9/38
US Classification:
712239, 712E09056
Abstract:
A method and apparatus to utilize a branch prediction scheme that limits the expenditure of power and the area consumed caused by branch prediction schemes is provided. The method includes accessing a first entry and a second entry of the data structure, wherein each entry stores a portion of a predicted target address, determining the predicted target address using the portion of the predicted target address stored in the first entry and a portion of a branch address of a fetched branch instruction for a fetched branch instruction of a first type, and determining the predicted target address using the portion of the predicted target address stored in the first entry and the portion of the predicted target address stored in the second entry for a fetched branch instruction of a second type.
Cumulative Confidence Fetch Throttling
US Patent:
2012012, May 17, 2012
Filed:
Nov 15, 2010
Appl. No.:
12/946491
Inventors:
Marvin Denman - Round Rock TX, US
James Dundas - Austin TX, US
Bradley Gene Burgess - Austin TX, US
Jeff Rupley - Round Rock TX, US
James Dundas - Austin TX, US
Bradley Gene Burgess - Austin TX, US
Jeff Rupley - Round Rock TX, US
International Classification:
G06F 9/38
US Classification:
712237, 712E09056
Abstract:
A method and apparatus to utilize a fetching scheme for instructions in a processor to limit the expenditure of power caused by the speculative execution of branch instructions is provided. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus. The method includes calculating a cumulative confidence measure based on one or more outstanding conditional branch instructions. The method also includes reducing prefetching operations in response to detecting that the cumulative confidence measure is below a first threshold level.
Method And Apparatus For Increasing Load Bandwidth
US Patent:
2010032, Dec 23, 2010
Filed:
Jun 15, 2010
Appl. No.:
12/816297
Inventors:
Rajesh Patel - Austin TX, US
James Dundas - Austin TX, US
Adi Yoaz - Austin TX, US
James Dundas - Austin TX, US
Adi Yoaz - Austin TX, US
International Classification:
G06F 9/46, G06F 12/00, G06F 12/08
US Classification:
718102, 711118, 711E12001, 711E12017
Abstract:
A method and apparatus for dual-target register allocation is described, intended to enable the efficient mapping/renaming of registers associated with instructions within a pipelined microprocessor architecture.
Method And Apparatus For Increasing Load Bandwidth
US Patent:
7739483, Jun 15, 2010
Filed:
Sep 28, 2001
Appl. No.:
09/968474
Inventors:
Rajesh Patel - Austin TX, US
James Dundas - Austin TX, US
Adi Yoaz - Austin TX, US
James Dundas - Austin TX, US
Adi Yoaz - Austin TX, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 7/38, G06F 9/00, G06F 9/44
US Classification:
712214, 712215, 712225, 711213
Abstract:
A method and apparatus for dual-target register allocation is described, intended to enable the efficient mapping/renaming of registers associated with instructions within a pipelined microprocessor architecture.