JAMES CLARENCE PARKER
Pilots at Sweetbriar Ln, Zionsville, PA
License number
Pennsylvania A4368733
Issued Date
Feb 2017
Expiration Date
Feb 2019
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
6581 Sweetbriar Ln, Zionsville, PA 18092
Professional information
System And Method For Employing Signoff-Quality Timing Analysis Information Concurrently In Multiple Scenarios To Reduce Dynamic Power In An Electronic Circuit And An Apparatus Incorporating The Same
US Patent:
2012022, Aug 30, 2012
Filed:
Feb 24, 2011
Appl. No.:
13/034167
Inventors:
Bruce Zahn - Allentown PA, US
James C. Parker - Zionsville PA, US
Benjamin Mbouombouo - Saratoga CA, US
James C. Parker - Zionsville PA, US
Benjamin Mbouombouo - Saratoga CA, US
International Classification:
G06F 17/50, G06F 9/455
US Classification:
716134
Abstract:
A dynamic power recovery system and method are disclosed herein. Additionally, an EDA tool and apparatus configured to perform dynamic power recovery are disclosed. In one embodiment, the system includes: (1) a power recovery module configured to carry out an instance of an initial power recovery process in each of multiple scenarios concurrently, the initial power recovery process including making first conditional downsizing of cells in at least one path in a circuit design with lower dynamic power cells and estimating a delay and a slack of the at least one path based on the first conditional downsizings and (2) a speed recovery module associated with the power recovery module and configured to carry out a speed recovery process in each of the multiple scenarios concurrently, the speed recovery process including determining whether the first conditional downsizings cause a timing violation with respect to the at least one path and making second conditional upsizings with higher dynamic power cells until the timing violation is removed.
Methods For Designing Integrated Circuits Employing Voltage Scaling And Integrated Circuits Designed Thereby
US Patent:
2010002, Feb 4, 2010
Filed:
Feb 3, 2009
Appl. No.:
12/364918
Inventors:
James C. Parker - Zionsville PA, US
Vishwas M. Rao - Breinigsville PA, US
Gregory W. Sheets - Breinigsville PA, US
Prasad Subbarao - San Jose CA, US
Vishwas M. Rao - Breinigsville PA, US
Gregory W. Sheets - Breinigsville PA, US
Prasad Subbarao - San Jose CA, US
Assignee:
Agere Systems, Inc. - Allentown PA
International Classification:
G05F 1/10, G06F 17/50
US Classification:
327538, 716 12, 716 18, 716 1
Abstract:
Various embodiments of methods of designing an integrated circuit (IC). One embodiment of one such method includes: (1) generating a functional design for the IC, (2) determining performance objectives for the IC, (3) determining an optimization target voltage for the IC, (4) determining whether the IC needs voltage scaling to achieve the performance objectives at the optimization target voltage and, if so, whether the IC is to employ static voltage scaling or adaptive voltage scaling, (5) using the optimization target voltage to implement a layout from the functional IC design that meets the performance objectives and (6) performing a timing signoff of the layout at the optimization target voltage.
Method For Designing Integrated Circuits Employing A Partitioned Hierarchical Design Flow And An Apparatus Employing The Method
US Patent:
8539419, Sep 17, 2013
Filed:
Mar 15, 2012
Appl. No.:
13/421710
Inventors:
Vishwas M. Rao - Breinigsville PA, US
James C. Parker - Zionsville PA, US
James C. Parker - Zionsville PA, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
G06F 17/50
US Classification:
716122, 716110, 716113, 716118, 716119, 716124, 716125
Abstract:
Methods of designing an IC and a hierarchical design flow generator are disclosed. In one embodiment, the method includes: (1) receiving timing and physical constraints for an IC design at an apparatus, (2) establishing a hierarchical design flow for providing an implementation of the IC design employing the apparatus and (3) partitioning the hierarchical design flow into a late design flow portion and an early design flow portion employing the apparatus, wherein the late design flow portion is substantially the same for different design flow methodologies.
Method For Designing Integrated Circuits Employing A Partitioned Hierarchical Design Flow And An Apparatus Employing The Method
US Patent:
8239805, Aug 7, 2012
Filed:
Jul 27, 2009
Appl. No.:
12/510104
Inventors:
Vishwas M. Rao - Breinigsville PA, US
James C. Parker - Zionsville PA, US
James C. Parker - Zionsville PA, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
G06F 17/50
US Classification:
716125, 716110, 716113, 716118
Abstract:
Methods of designing an IC and a hierarchical design flow generator are disclosed. In one embodiment, a method includes: (1) partitioning a design implementation flow for an IC into a late design flow portion and an early design flow portion employing a processor, (2) dividing components of the late design flow portion and the early design flow portion into a functional block implementation section and a top level implementation section employing the processor, (3) aligning dependencies between the functional block implementation sections and the top level implementation sections in both of the early design flow portion and the late design flow portion employing the processor and (4) implementing a layout for the IC based on the early and the late design flow portions employing the processor.
Method For Designing Integrated Circuits Employing Correct-By-Construction Progressive Modeling And An Apparatus Employing The Method
US Patent:
2014005, Feb 27, 2014
Filed:
Aug 22, 2012
Appl. No.:
13/592169
Inventors:
Gerard M. Blair - Bath PA, US
Shirley V. Smith - Allentown PA, US
James C. Parker - Zionsville PA, US
Vishwas Rao - Breinigsville PA, US
Joseph J. Jamann - Nazareth PA, US
Bruce E. Zahn - Allentown PA, US
Tammy L. Harkness - Barto PA, US
Shirley V. Smith - Allentown PA, US
James C. Parker - Zionsville PA, US
Vishwas Rao - Breinigsville PA, US
Joseph J. Jamann - Nazareth PA, US
Bruce E. Zahn - Allentown PA, US
Tammy L. Harkness - Barto PA, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
G06F 17/50
US Classification:
716108
Abstract:
Methods of designing an integrated circuit and an apparatus for designing an integrated circuit are disclosed herein. In one embodiment, a method includes: (1) generating a block model of the integrated circuit according to a first timing budget, (2) developing a top level implementation of the integrated circuit according to the first timing budget, (3) determining a second timing budget for the integrated circuit based on the block model and (4) modifying the block model and the top level implementation employing the second timing budget to provide a progressive block model and a modified top level implementation.
Systematic, Normalized Metric For Analyzing And Comparing Optimization Techniques For Integrated Circuits Employing Voltage Scaling And Integrated Circuits Designed Thereby
US Patent:
8281266, Oct 2, 2012
Filed:
Feb 3, 2009
Appl. No.:
12/365010
Inventors:
Joseph J. Jamann - Nazareth PA, US
James C. Parker - Zionsville PA, US
Vishwas M. Rao - Breinigsville PA, US
James C. Parker - Zionsville PA, US
Vishwas M. Rao - Breinigsville PA, US
Assignee:
Agere Systems LLC - Wilmington DE
International Classification:
G06F 17/50
US Classification:
716108, 716109
Abstract:
Various embodiments of methods of designing an integrated circuit (IC). One embodiment of one such method includes: (1) generating a functional design for the IC, (2) determining performance objectives for the IC, (3) determining an optimization target voltage for the IC, (4) determining whether the IC needs voltage scaling to achieve the performance objectives at the optimization target voltage and, if so, whether the IC is to employ static voltage scaling or adaptive voltage scaling, (5) using the optimization target voltage to synthesize a layout from the functional IC design that meets the performance objectives by employing a unitless performance/power quantifier as a metric to gauge a degree of optimization thereof and (6) performing a timing signoff of the layout at the optimization target voltage.
Modifying Integrated Circuit Designs To Achieve Multiple Operating Frequency Targets
US Patent:
7930674, Apr 19, 2011
Filed:
Mar 29, 2007
Appl. No.:
11/693081
Inventors:
James C. Parker - Zionsville PA, US
Vishwas Rao - Breinigsville PA, US
Vishwas Rao - Breinigsville PA, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
G06F 17/50
US Classification:
716134
Abstract:
A first integrated circuit design with a first maximum operating frequency is modified to achieve a second integrated circuit design with a second maximum operating frequency. The integrated circuit design comprises an arrangement of cells. Each of these cells drives a signal that propagates through a net of other circuit elements to one or more nodes that are limited by respective signal timing constraints. An analytical cost function is assigned to each of the cells. Each analytical cost function comprises a value for its respective cell that is based on one or more speed-related factors indicative of the impact of the respective cell on the first maximum operating frequency of the first integrated circuit design. One or more of the cells are replaced with different cells based on the determined analytical cost functions.
Methods For Designing Integrated Circuits Employing Pre-Determined Timing-Realizable Clock-Insertion Delays And Integrated Circuit Design Tools
US Patent:
2012001, Jan 12, 2012
Filed:
Jul 6, 2010
Appl. No.:
12/831038
Inventors:
Vishwas M. Rao - Breinigsville PA, US
James C. Parker - Zionsville PA, US
James C. Parker - Zionsville PA, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
G06F 17/50
US Classification:
716113
Abstract:
A method of designing an integrated circuit, an EDA tool, an apparatus and a computer-readable medium are disclosed herein. In one embodiment, the method includes: (1) generating a set of constraint equations representing clock-insertion delay values for the integrated circuit as variables, (2) determining bounds on each of the clock-insertion delay values based on the constraint equations and (3) generating a set of closing commands based on the bounds for driving a design of the integrated circuit to closure, wherein each step of the method is carried out by at least one EDA tool.
Systematic Benchmarking System And Method For Standardized Data Creation, Analysis And Comparison Of Semiconductor Technology Node Characteristics
US Patent:
8307324, Nov 6, 2012
Filed:
Aug 18, 2011
Appl. No.:
13/212427
Inventors:
Joseph J. Jamann - Nazareth PA, US
James C. Parker - Zionsville PA, US
Vishwas M. Rao - Breinigsville PA, US
James C. Parker - Zionsville PA, US
Vishwas M. Rao - Breinigsville PA, US
Assignee:
Agere Systems LLC - Wilmington DE
International Classification:
G06F 17/50
US Classification:
716132, 716136, 703 14
Abstract:
One aspect provides a method of standardized data creation and analysis of semiconductor technology node characteristics. In one embodiment, the method includes: (1) designing representative benchmark circuits for a clock path, a data path and a flip-flop path, (2) establishing at least one standard sensitization and measurement rule for delay and power for the representative benchmark circuits and across corners in the technology nodes, (3) performing a simulation by sweeping through a range of values and at predetermined intervals across the corners, (4) extracting data from the simulation, (5) writing the data to a databank and (6) parsing and interpreting the data to produce at least one report.
Systematic Benchmarking System And Method For Standardized Data Creation, Analysis And Comparison Of Semiconductor Technology Node Characteristics
US Patent:
8024694, Sep 20, 2011
Filed:
Feb 3, 2009
Appl. No.:
12/365084
Inventors:
Joseph J. Jamann - Nazareth PA, US
James C. Parker - Zionsville PA, US
Vishwas M. Rao - Breinigsville PA, US
James C. Parker - Zionsville PA, US
Vishwas M. Rao - Breinigsville PA, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
G06F 17/50
US Classification:
716132, 716136, 703 14
Abstract:
One aspect provides a method of standardized data creation and analysis of semiconductor technology node characteristics. In one embodiment, the method includes: (1) designing at least one representative benchmark circuit, (2) establishing standard sensitization and measurement rules for delay and power for the at least one representative benchmark circuit and across corners in the technology nodes, (3) performing a simulation by sweeping through a range of values and at predetermined intervals across the corners, (4) extracting data from the simulation and (5) parsing and interpreting the data to produce at least one report.