JAMES CARROLL BRADY, MS PT
Physical Therapy in Dallas, TX

5331228, Jul 19, 1994

Jul 31, 1992

7/923135

James Brady - Dallas TX

SGS-Thomson Microelectronics, Inc. - Carrollton TX

H03K 1900, H03K 190948

307473

An output driver circuit includes a sense amplifier coupled to a first inverter and a second inverter. The first and second inverters drive a first and second chain of logic gates, respectively. A p-channel output transistor is coupled to the output of the first chain of logic gates, and an n-channel output transistor is coupled to the output of the second chain of logic gates. The transistors in the first and second inverters are selected so that the first inverter and the second inverter have complementary preferential output states. The first and second inverters generate their preferential output state in response to a selected intermediate output voltage range from the sense amplifier to turn off both the n-channel transistor and the p-channel transistor. This causes the n-channel and p-channel output transistors to both turn off when the sense amplifier generates the intermediate voltage during an equilibrate period.

5099148, Mar 24, 1992

Oct 22, 1990

7/601288

David C. McClure - Carrollton TX
James Brady - Dallas TX

SGS-Thomson Microelectronics, Inc. - Carrollton TX

H03K 1716

307443

An output driver arrangement for an integrated circuit having multiple output terminals is disclosed. Each of the output drivers is a push-pull driver, with the gates of the pull-up and pull-down transistors each controlled by a logic circuit; the logic circuits perform a logical combination of the data to be presented and an output disable signal. In order to control the switching speed of the outputs, and thus to reduce induced noise, each of the logic circuits share a resistor network at their bias nodes. For example, each of the logic circuits controlling the pull-up device share a resistor network for bias from V. sub. cc, and a resistor network for bias to ground; similarly, each of the logic circuits controlling the pull-down device share a resistor network for bias from V. sub. cc and a resistor network for bias to ground. Various arrangements including fuses may be used to allow selection of the resistance value of each of the networks, according to the performance of the circuit or in response to product demand.

5311467, May 10, 1994

Apr 7, 1992

7/864481

Mark A. Lysinger - Carrollton TX
William C. Slemmer - Dallas TX
James Brady - Dallas TX
David C. McClure - Carrollton TX

SGS-Thomson Microelectronics, Inc. - Carrollton TX

G11B 700

36518901

A memory is disclosed having a plurality of memory cells in a memory array arranged in rows and columns, each of the memory cells capable of storing a logic state therein. Each pair of bit lines is associated with one of the columns. A column decoder selects a column in the array responsive to a column address. A plurality of word line drivers selects, in response to a row address, a row of memory cells for connection with their associated pair of bit lines. A plurality of row isolation circuits isolates and enables a selected group of memory cells of each row from the remainder of the row in response to a bulk write signal. Each row isolation circuit has a conduction path between its associated word line driver and the selected memory cells in the associated row. A bulk write signal is sent to each column containing the selected memory cells. A first logic state is then written into the selected memory cells in response to the bulk write signal.

5644542, Jul 1, 1997

Jun 2, 1995

8/460409

David Charles McClure - Carrollton TX
James Brady - Dallas TX

SGS-Thomson Microelectronics, Inc. - Carrollton TX

G11C 700

365201

A method for stress testing a memory array in an integrated circuit. Control circuitry selects a plurality of row lines at one time. An overvoltage suitable for stressing the cells of the array is placed on the bit lines. Because a block of cells has been selected, the overvoltage is applied to all cells of the block. The block of cells selected may be either the entire memory array or a portion of the memory array. The selected rows remain selected for the duration of the stress test. Because the overvoltage is applied directly to selected cells, the full overvoltage will be used to stress the transistor gates for the entire test period. In this manner, latent defects within the memory array can be detected.

5151387, Sep 29, 1992

Apr 30, 1990

7/516272

James Brady - Dallas TX
Tsiu C. Chan - Carrollton TX
David S. Culver - The Colony TX

SGS-Thomson Microelectronics, Inc. - Carrollton TX

H01L 2144

437191

A contact structure provides electrical contact between two polycrystalline silicon interconnect layers. The lower layer has a silicide layer on its upper surface. The upper polycrystalline silicon layer can be doped with a different conductivity type, and makes an ohmic contact with the silicided region of the lower polycrystalline silicon layer.