JAMES BRADLEY DAVIS, SR
Pilots at Tow Path Ln, Richmond, VA

7107507, Sep 12, 2006

Mar 8, 2002

10/093832

James Andrew Davis - Richmond VA, US
Jonathan Jedwab - London, GB
Stephen Morley - Thornbury, GB
Kenneth Graham Paterson - Teddington, GB

Hewlett-Packard Development Company, L.P. - Houston TX

G11C 29/00, G11C 11/00, G11C 8/00

714763, 365158, 36523003

A magnetoresistive solid-state storage device (MRAM device) uses storage cells arranged in many arrays to form a macro-array For fast access times and to reduce exposure to physical failures, each unit of data (e. g. a sector) is stored with a few sub-units (e. g. bytes) in each of a large plurality of the arrays Advantageously, the plurality of arrays are accessible in parallel substantially simultaneously, and a failure in any one array affects only a small portion of the data unit. Optionally, error correction coding (ECC) is employed to form encoded data with symbols which are stored according to preferred embodiments which further minimise exposure to physical failures.

7107508, Sep 12, 2006

Mar 8, 2002

10/093851

Jonathan Jedwab - London, GB
James Andrew Davis - Richmond VA, US
Kenneth Graham Paterson - Teddington, GB
Gadiel Seroussi - Cupertino CA, US

Hewlett-Packard Development Company, L.P. - Houston TX

G11C 29/00

714763

A fault-tolerant magnetoresistive solid-state storage device (MRAM) in use performs error correction coding and decoding of stored information, to tolerate physical failures. At manufacture, the device is tested to confirm that each set of storage cells is suitable for storing ECC encoded data. The test comprises identifying failed cells where the failures will be visible in use for the generation of erasure information used in ECC decoding, by comparing parametric values obtained from the cells against one or more failure ranges, and includes performing a write-read-compare operation with test data to identify failed cells which will be hidden for the generation of erasure information in use. A failure count is formed based on both the visible failures and the hidden failures, to determine that the set of cells is suitable for storing ECC encoded data. The failure count is weighted, with hidden failures having a greater weighting than visible failures.

2004014, Jul 22, 2004

Jul 30, 2003

10/632130

David Banks - Bristol, GB
James Davis - Richmond VA, US
Jonathan Jedwab - Vancouver, CA

G11C007/00

365/200000

An MRAM solid-state storage device is disclosed having at least one array of magnetoresistive storage cells. The MRAM device includes a Reed-Solomon encoder arranged to encode original data to generate one or more codewords of length B symbols including 2T check symbols, using a generator polynomial G(x) of the form: where 0L

7418644, Aug 26, 2008

Mar 1, 2004

10/790360

Kenneth Kay Smith - Boise ID, US
Jonathan Jedwab - Vancouver, CA
James A. Davis - Richmond VA, US
David Banks - Bristol, GB
Stewart R. Wyatt - Boise ID, US

Hewlett-Packard Development Company, L.P. - Houston TX

H03M 13/29

714755

A system for error correction coding and decoding information is disclosed. In one embodiment, the first and second encoders are each configured to encode the information, wherein the second encoder has a higher capability than the first encoder. First and second decoders are configured to recover the information, wherein the second decoder recovers the information encoded by the second encoder only if the first decoder cannot recover the information.

2003002, Jan 30, 2003

Jul 25, 2001

09/915179

James Davis - Richmond VA, US
Kenneth Eldredge - Boise ID, US
Jonathan Jedwab - Bristol, GB
Dominic McCarthy - Mountain View CA, US
Stephen Morley - Bristol, GB
Kenneth Paterson - Teddington, GB
Frederick Perner - Palo Alto CA, US
Kenneth Smith - Boise ID, US
Stewart Wyatt - Boise ID, US

G11C029/00

714/763000

A magnetoresistive solid-state storage device (MRAM) performs error correction coding (ECC) of stored information. At manufacture or during use, each logical block of ECC encoded data and/or the corresponding set of storage cells are evaluated to determine suitability for continued use, or whether remedial action is necessary. In a first preferred method ECC decoding is attempted to determine whether information is unrecoverable from the block of ECC encoded data. In a second preferred method a parametric evaluation is made prior to attempting ECC decoding.

6999366, Feb 14, 2006

Dec 3, 2003

10/727273

Frederick A. Perner - Palo Alto CA, US
Jonathan Jedwab - Vancouver, CA
James A. Davis - Richmond VA, US
David McIntyre - Boise ID, US
David Banks - Bristol, GB
Stewart Wyatt - Boise ID, US
Kenneth K. Smith - Boise ID, US

Hewlett-Packard Development Company, LP. - Houston TX

G11C 7/02

365209, 365158

Embodiments of the present invention provide a magnetic memory. In one embodiment, the magnetic memory comprises an array of memory cells configured to provide resistive states, and a read circuit. The read circuit is configured to sense a resistance through a memory cell in the array of memory cells to obtain a sense result and categorize the sense result into one of at least three different categories comprising a middle category situated between the resistive states.