JAMES BERNARD KELLER
Pilots at Palomar Dr, Redwood City, CA

8301941, Oct 30, 2012

Nov 28, 2011

13/305202

Luka Bodrozic - San Francisco CA, US
Sukalpa Biswas - Fremont CA, US
Hao Chen - San Ramon CA, US
Sridhar P. Subramanian - Cupertino CA, US
James B. Keller - Redwood City CA, US

Apple Inc. - Cupertino CA

G01R 31/28, G11C 29/00, G06F 11/00

714716, 714718, 714743

An apparatus may include an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller may be programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller may be configured to receive a first write operation from the processor over the interconnect. The memory controller may be configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller may be further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.

8086915, Dec 27, 2011

Oct 21, 2010

12/909073

Luka Bodrozic - San Francisco CA, US
Sukalpa Biswas - Fremont CA, US
Hao Chen - San Ramon CA, US
Sridhar P. Subramanian - Cupertino CA, US
James B. Keller - Redwood City CA, US

Apple Inc. - Cupertino CA

G01R 31/28, G11C 29/00, G06F 11/00

714716, 714719, 714743

In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect. The memory controller is configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller is further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.

7346078, Mar 18, 2008

Jan 31, 2003

10/356324

Manu Gulati - Santa Clara CA, US
Laurent Moll - Saratoga CA, US
James Keller - Redwood City CA, US

Broadcom Corporation - Irvine CA

H04J 3/22

370469, 370474

A multiple processor device stores a stream of data as a plurality of data segments, which includes multiplexed data fragments from at least one of a plurality of virtual channels. The data segments that comprise the stream of data correspond to the multiplexed data fragments from the virtual channels. The multiple processor device then decodes at least one data segment in accordance with one of a plurality of transmission protocols to produce a decoded data segment. The multiple processor device then stores the decoded data segment to align it in accordance with a data path segment size. The multiple processor device then interprets the stored decoded data segment with respect to a corresponding one of the plurality of virtual channels to determine a destination of the stored decoded data segment. The multiple processor device then stores the decoded data segment as part of reassembled data.

2013015, Jun 13, 2013

Jan 31, 2013

13/755999

Apple Inc. - Cupertino CA, US
Zongjian Chen - Palo Alto CA, US
James B. Keller - Redwood City CA, US
Timothy J. Millet - Mountain View CA, US

Apple Inc. - Cupertino CA

G06F 12/12, G06F 12/08

711128

In an embodiment, a cache stores tags for cache blocks stored in the cache. Each tag may include an indication identifying which of two or more replacement policies supported by the cache is in use for the corresponding cache block, and a replacement record indicating the status of the corresponding cache block in the replacement policy. Requests may include a replacement attribute that identifies the desired replacement policy for the cache block accessed by the request. If the request is a miss in the cache, a cache block storage location may be allocated to store the corresponding cache block. The tag associated with the cache block storage location may be updated to include the indication of the desired replacement policy, and the cache may manage the block in accordance with the policy. For example, in an embodiment, the cache may support both an LRR and an LRU policy.

8392658, Mar 5, 2013

Jul 10, 2009

12/500768

James Wang - Vista CA, US
Zongjian Chen - Palo Alto CA, US
James B. Keller - Redwood City CA, US
Timothy J. Millet - Mountain View CA, US

Apple Inc. - Cupertino CA

G06F 12/00

711128, 711118, 711130, 711133, 711136, 711141, 711146, 711147

In an embodiment, a cache stores tags for cache blocks stored in the cache. Each tag may include an indication identifying which of two or more replacement policies supported by the cache is in use for the corresponding cache block, and a replacement record indicating the status of the corresponding cache block in the replacement policy. Requests may include a replacement attribute that identifies the desired replacement policy for the cache block accessed by the request. If the request is a miss in the cache, a cache block storage location may be allocated to store the corresponding cache block. The tag associated with the cache block storage location may be updated to include the indication of the desired replacement policy, and the cache may manage the block in accordance with the policy. For example, in an embodiment, the cache may support both an LRR and an LRU policy.

8078772, Dec 13, 2011

Oct 20, 2010

12/908605

James Wang - Milpitas CA, US
Zongjian Chen - Palo Alto CA, US
James B. Keller - Redwood City CA, US

Apple Inc. - Cupertino CA

G06F 13/00, H03K 5/135

710 52

In one embodiment, an apparatus comprises a first clocked storage device operable in a first clock domain corresponding to a first clock signal. The first clocked storage device has an input coupled to receive one or more bits transmitted on the input from a second clock domain corresponding to a second clock signal. The apparatus further comprises control circuitry configured to ensure that a change in a value of the one or more bits transmitted on the input meets setup and hold time requirements of the first clocked storage device. The control circuitry is responsive to a sample history of one of the first clock signal or the second clock signal to detect a phase relationship between the first clock signal and the second clock signal on each clock cycle to ensure the change meets the setup and hold time requirements.

7647518, Jan 12, 2010

Oct 10, 2006

11/546223

Po-Yung Chang - Saratoga CA, US
Wei-Han Lien - San Jose CA, US
Jesse Pan - San Jose CA, US
Ramesh Gunna - San Jose CA, US
Tse-Yu Yeh - Cupertino CA, US
James B. Keller - Redwood City CA, US

Apple Inc. - Cupertino CA

G06F 1/32, G06F 9/38

713320, 712215

In one embodiment, a processor comprises a scheduler configured to issue a first instruction operation to be executed and an execution core coupled to the scheduler. Configured to execute the first instruction operation, the execution core comprises a plurality of replay sources configured to cause a replay of the first instruction operation responsive to detecting at least one of a plurality of replay cases. The scheduler is configured to inhibit issuance of the first instruction operation subsequent to the replay for a subset of the plurality of replay cases. The scheduler is coupled to receive an acknowledgement indication corresponding to each of the plurality of replay cases in the subset, and is configured to inhibit issuance of the first instruction operation until the acknowledge indication is asserted that corresponds to an identified replay case of the subset.

2008008, Apr 10, 2008

Oct 10, 2006

11/545825

Po-Yung Chang - Saratoga CA, US
Ramesh Gunna - San Jose CA, US
Tse-Yu Yeh - Cupertino CA, US
James B. Keller - Redwood City CA, US

P.A. Semi, Inc. - Santa Clara CA

G06F 12/00

711118

In one embodiment, a processor comprises a buffer and a control unit coupled to the buffer. The buffer is configured to store requests to be transmitted on an interconnect on which the processor is configured to communicate. The buffer is coupled to receive a first uncacheable load request having a first address. The control unit is configured to merge the first uncacheable load request with a second uncacheable load request that is stored in the buffer responsive to a second address of the second load request matching the first address within a granularity. A single transaction on the interconnect is used for both the first and second uncacheable load requests, if merged. Separate transactions on the interconnect are used for each of the first and second uncacheable load requests if not merged.

8171326, May 1, 2012

May 24, 2010

12/785842

James B. Keller - Redwood City CA, US
Tse-Yu Yeh - Cupertino CA, US
Ramesh Gunna - San Jose CA, US
Brian J. Campbell - Sunnyvale CA, US

Apple Inc. - Cupertino CA

G06F 1/32

713324

In one embodiment, a processor comprises a data cache configured to store a plurality of cache blocks and a control unit coupled to the data cache. The control unit is configured to flush the plurality of cache blocks from the data cache responsive to an indication that the processor is to transition to a low power state in which one or more clocks for the processor are inhibited.

8359414, Jan 22, 2013

Jun 21, 2011

13/165235

James B. Keller - Redwood City CA, US
Sridhar P. Subramanian - Cupertino CA, US
Ramesh Gunna - San Jose CA, US

Apple Inc. - Cupertino CA

G06F 3/00, G06F 15/167

710 52, 709214

An interface unit may comprise a buffer configured to store requests that are to be transmitted on an interconnect and a control unit coupled to the buffer. In one embodiment, the control unit is coupled to receive a retry response from the interconnect during a response phase of a first transaction for a first request stored in the buffer. The control unit is configured to record an identifier supplied on the interconnect with the retry response that identifies a second transaction that is in progress on the interconnect. The control unit is configured to inhibit reinitiation of the first transaction at least until detecting a second transmission of the identifier. In another embodiment, the control unit is configured to assert a retry response during a response phase of a first transaction responsive to a snoop hit of the first transaction on a first request stored in the buffer for which a second transaction is in progress on the interconnect. The control unit is further configured to provide an identifier of the second transaction with the retry response.