JAMES B WILLIAMS, M.D.
Osteopathic Medicine at Sloan Pl, Saint Paul, MN

7096322, Aug 22, 2006

Oct 10, 2003

10/683028

Jason D. Sollom - Champlin MN, US
James A. Williams - Mahtomedi MN, US

Unisys Corporation - Blue Bell PA

G06F 12/02

711143

Techniques are described for accurately and efficiently emulating an instruction processor having a write buffer. The described techniques may be utilized to quickly develop an emulated instruction processor that provides a fully-functional write buffer interface in an efficient and elegant manner. For example, a system is described that includes a computing system that provides an emulation environment, and software executing within the emulation environment that emulates an instruction processor having a write buffer interface and a memory interface. The software emulates the instruction processor by selectively outputting a write request on the write buffer interface or the memory interface in response to an emulation control instruction embedded within an instruction stream.

7065614, Jun 20, 2006

Jun 20, 2003

10/600880

Kelvin S. Vartti - Hugo MN, US
James A. Williams - Mahtomedi MN, US
Donald C. Englin - Shoreview MN, US

Unisys Corporation - Blue Bell PA

G06F 12/00, G06F 13/00

711141, 711135, 711152, 711159

The current invention provides a system and method for maintaining memory coherency within a multiprocessor environment that includes multiple requesters such as instruction processors coupled to a shared main memory. Within the system of the current invention, data may be provided from the shared memory to a requester for update purposes before all other read-only copies of this data stored elsewhere within the system have been invalidated. To ensure that this acceleration mechanism does not result in memory incoherency, an instruction is provided for inclusion within the instruction set of the processor. Execution of this instruction causes the executing processor to discontinue execution until all outstanding invalidation activities have completed for any data that has been retrieved and updated by the processor.

6934810, Aug 23, 2005

Sep 26, 2002

10/255276

James A. Williams - Mahtomedi MN, US
Robert H. Andrighetti - Somerset WI, US
Kelvin S. Vartti - Hugo MN, US
David P. Williams - Mounds View MN, US

Unisys Corporation - Blue Bell PA

G06F012/00

711137, 711133, 711135

A mechanism to selectively leak data signals from a cache memory is provided. According to one aspect of the invention, an Instruction Processor (IP) is coupled to generate requests to access data signals within the cache. Some requests include a leaky designator, which is activated if the associated data signals are considered “leaky”. These data signals are flushed from the cache memory after a predetermined delay has occurred. The delay is provided to allow the IP to complete any subsequent requests for the same data before the flush operation is performed, thereby preventing memory thrashing. Pre-fetch logic may also be provided to pre-fetch the data signals associated with the requests. In one embodiment, the rate at which data signals are flushed from cache memory is programmable, and is based on the rate at which requests are processing for pre-fetch purposes.

7228266, Jun 5, 2007

Dec 5, 2003

10/729666

Jason D. Sollom - Champlin MN, US
James A. Williams - White Bear Lake MN, US

Unisys Corporation - Blue Bell PA

G06F 9/455

703 26, 717118, 717138, 717148, 703 23, 703 28

Techniques are described for emulating an instruction processor for use during the development of a computer system. Specifically, the techniques describe an emulated instruction processor that accurately and efficiently emulates an instruction processor having separate interfaces to fetch op-codes and operands. Further, the emulated instruction processor may provide detection of errors associated with the separate interfaces. By making use of the techniques described herein, detailed information relating to errors associated with the memory architecture may be gathered for use in verifying components within the memory architecture, such as first and second-level caches.

7356650, Apr 8, 2008

Jun 17, 2005

11/156225

Donald C. Englin - Shoreview MN, US
James A. Williams - White Bear Lake MN, US

Unisys Corporation - Blue Bell PA

G06F 12/00

711138, 711136, 711139, 711134

Systems and methods are provided for a data processing system and a cache arrangement. The data processing system includes at least one processor, a first-level cache, a second-level cache, and a memory arrangement. The first-level cache bypasses storing data for a memory request when a do-not-cache attribute is associated with the memory request. The second-level cache stores the data for the memory request. The second-level cache also bypasses updating of least-recently-used indicators of the second-level cache when the do-not-cache attribute is associated with the memory request.

6973541, Dec 6, 2005

Sep 26, 2002

10/255495

James A. Williams - Mahtomedi MN, US
Robert H. Andrighetti - Somerset WI, US
Conrad S. Shimada - Oakdale MN, US
Kelvin S. Vartti - Hugo MN, US
Stephen Sutter - Osseo MN, US
Chad M. Sonmore - Blaine MN, US

Unisys Corporation - Blue Bell PA

G06F012/00

711135, 711118

An improved system and method are provided for initializing memory in a data processing system. According to one aspect of the invention, a “page zero” instruction is provided that may be executed by an Instruction Processor to initiate memory initialization. Upon instruction execution, the IP issues one or more page zero requests using a background interface of the IP. In one embodiment, each request results in the initialization of a page of memory. While page zero requests are issued over the background interface, the IP may continue issuing other read and write requests to memory over a primary interface of the IP.

6976128, Dec 13, 2005

Sep 26, 2002

10/255420

James A. Williams - Mahtomedi MN, US
Robert H. Andrighetti - Somerset WI, US
Conrad S. Shimada - Oakdale MN, US
Donald C. Englin - Shoreview MN, US

Unisys Corporation - Blue Bell PA

G06F012/00

711135, 711141

A system and method is provided to selectively flush data from cache memory to a main memory irrespective of the replacement algorithm that is used to manage the cache data. According to one aspect of the invention, novel “page flush” and “cache line flush” instructions are provided to flush a page and a cache line of memory data, respectively, from a cache to a main memory. In one embodiment, these instructions are included within the hardware instruction set of an Instruction Processor (IP). According to another aspect of the invention, flush operations are initiated using a background interface that interconnects the IP with its associated cache memory. A primary interface that also interconnects the IP to the cache memory is used to simultaneously issue higher-priority requests so that processor throughput is increased.

6993630, Jan 31, 2006

Sep 26, 2002

10/255393

James A. Williams - Mahtomedi MN, US
Robert H. Andrighetti - Somerset WI, US
Conrad S. Shimada - Oakdale MN, US
Donald C. Englin - Shoreview MN, US
Kelvin S. Vartti - Hugo MN, US

Unisys Corporation - Blue Bell PA

G06F 12/00

711137, 711118

A system and method for pre-fetching data signals is disclosed. According to one aspect of the invention, an Instruction Processor (IP) generates requests to access data signals within the cache. Predetermined ones of the requests are provided to pre-fetch control logic, which determines whether the data signals are available within the cache. If not, the data signals are retrieved from another memory within the data processing system, and are stored to the cache. According to one aspect, the rate at which pre-fetch requests are generated may be programmably selected to match the rate at which the associated requests to access the data signals are provided to the cache. In another embodiment, pre-fetch control logic receives information to generate pre-fetch requests using a dedicated interface coupling the pre-fetch control logic to the IP.