JAMES ARTHUR MCDONALD
Pilots at Bryant St, Palo Alto, CA
License number
California A3542266
Issued Date
Sep 2015
Expiration Date
Sep 2016
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
555 Bryant St #256, Palo Alto, CA 94301
Professional information
Disk Array Controller, And Components Thereof, For Use With Ata Disk Drives
US Patent:
6421760, Jul 16, 2002
Filed:
Apr 26, 2000
Appl. No.:
09/558524
Inventors:
James Arthur McDonald - Palo Alto CA
John Peter Herz - Los Altos CA
Mitchell Allen Altman - San Francisco CA
John Peter Herz - Los Altos CA
Mitchell Allen Altman - San Francisco CA
Assignee:
3ware, Inc. - Palo Alto CA
International Classification:
G06F 1200
US Classification:
711114, 711105, 711112
Abstract:
A high performance RAID system for a PC comprises a controller card which controls an array of ATA disk drives. The controller card includes an array of automated disk drive controllers, each of which controls one respective disk drive. The disk drive controllers are connected to a microcontroller by a control bus and are connected to an automated coprocessor by a packet-switched bus. The coprocessor accesses system memory and a local buffer. In operation, the disk drive controllers respond to controller commands from the microcontroller by accessing their respective disk drives, and by sending packets to the coprocessor over the packet-switched bus. The packets carry I/O data (in both directions, with the coprocessor filling-in packet payloads on I/O writes), and carry transfer commands and target addresses that are used by the coprocessor to access the buffer and system memory. The packets also carry special completion values (generated by the microcontroller) and I/O request identifiers that are processed by a logic circuit of the coprocessor to detect the completion of processing of each I/O request. The coprocessor grants the packet-switched bus to the disk drive controllers using a round robin arbitration protocol which guarantees a minimum I/O bandwidth to each disk drive.
Disk Array Controller With Automated Processor Which Routes I/O Data According To Addresses And Commands Received From Disk Drive Controllers
US Patent:
6138176, Oct 24, 2000
Filed:
Mar 4, 1998
Appl. No.:
9/034248
Inventors:
James Arthur McDonald - Palo Alto CA
John Peter Herz - Los Altos CA
Mitchell Allen Altman - San Francisco CA
William Edward Smith - Hayward CA
John Peter Herz - Los Altos CA
Mitchell Allen Altman - San Francisco CA
William Edward Smith - Hayward CA
Assignee:
3WARE - Palo Alto CA
International Classification:
G06F 300
US Classification:
710 6
Abstract:
A high-performance RAID system for a PC comprises a controller card which controls an array of ATA disk drives. The controller card includes an array of automated disk drive controllers, each of which controls one respective disk drive. The disk drive controllers are connected to a microcontroller by a control bus and are connected to an automated coprocessor by a packet-switched bus. The coprocessor accesses system memory and a local buffer. In operation, the disk drive controllers respond to controller commands from the microcontroller by accessing their respective disk drives, and by sending packets to the coprocessor over the packet-switched bus. The packets carry I/O data (in both directions, with the coprocessor filling-in packet payloads on I/O writes), and carry transfer commands and target addresses that are used by the coprocessor to access the buffer and system memory. The packets also carry special completion values (generated by the microcontroller) and I/O request identifiers that are processed by a logic circuit of the coprocessor to detect the completion of processing of each I/O request. The coprocessor grants the packet-switched bus to the disk drive controllers using a round robin arbitration protocol which guarantees a minimum I/O bandwidth to each disk drive.
Disk Drive Data Protection Using Clusters Containing Error Detection Sectors
US Patent:
6751757, Jun 15, 2004
Filed:
Dec 7, 2000
Appl. No.:
09/732244
Inventors:
Richard J. Biskup - Sunnyvale CA
Brian R. Davis - Sunnyvale CA
James A. McDonald - Palo Alto CA
Robert W. Horst - Saratoga CA
Brian R. Davis - Sunnyvale CA
James A. McDonald - Palo Alto CA
Robert W. Horst - Saratoga CA
Assignee:
3Ware - Sunnyvale CA
International Classification:
G06F 1108
US Classification:
714 54, 714 52, 714 53, 714701, 711112
Abstract:
The present invention is related to methods and apparatus that can enhance the reliability of a hard drive by providing a built-in error check in the drive. Conventional hard drives can erroneously seek to an incorrect location on a platter of the hard drive. The erroneous seek corrupts the data stream and is difficult to detect and correct. Embodiments of the present invention can detect a logical block address assigned to a portion of the platter of the hard drive and thereby detect when an erroneous seek has occurred. Upon detection of an error, one embodiment of the present invention can further take corrective action to read from the correct portion of the platter.
Methods And Systems For Selecting Block Sizes For Use With Disk Arrays
US Patent:
6591339, Jul 8, 2003
Filed:
Sep 8, 1999
Appl. No.:
09/392364
Inventors:
Robert W. Horst - Saratoga CA
William J. Alessi - San Francisco CA
James A. McDonald - Palo Alto CA
Rod S. Thompson - Sunnyvale CA
William J. Alessi - San Francisco CA
James A. McDonald - Palo Alto CA
Rod S. Thompson - Sunnyvale CA
Assignee:
3ware, Inc. - Mountain View CA
International Classification:
G06F 1202
US Classification:
711114, 714 6
Abstract:
The present invention is related to methods and systems for improving the read performance of a drive array, such as a RAID array, having an ânâ number of drives so that the read performance is greater than (n-1) times that of an independent single drive. Formatting information for each of at least three drives is received. A first parity block size for use with corresponding first zones of the at least three drives is selected. A second parity block size different than the first parity block size is selected for use with corresponding second zones of the at least three drives. The first and the second parity block sizes are selected to increase the read performance from the drive array based on at least a portion of the formatting information.
Methods And Systems For Mirrored Disk Arrays
US Patent:
6591338, Jul 8, 2003
Filed:
Sep 8, 1999
Appl. No.:
09/392363
Inventors:
Robert W. Horst - Saratoga CA
William J. Alessi - San Francisco CA
James A. McDonald - Palo Alto CA
Rod S. Thompson - Sunnyvale CA
William J. Alessi - San Francisco CA
James A. McDonald - Palo Alto CA
Rod S. Thompson - Sunnyvale CA
Assignee:
3ware, Inc. - Mountain View CA
International Classification:
G06F 1202
US Classification:
711114, 711153, 711173, 714 6
Abstract:
The present invention is related to methods and systems for providing different stripe sizes for different zones for at least a first of a plurality of mirrored drives to improve data rates. The first drive has a plurality of zones. In one embodiment, a first stripe size is selected for a first zone, and a second stripe size is selected for a second zone. The said second stripe size is different than said first stripe size.
System And Method For Processing And Tracking The Completion Of I/O Requests In A Disk Array System
US Patent:
6301625, Oct 9, 2001
Filed:
May 31, 2000
Appl. No.:
9/583293
Inventors:
James Arthur McDonald - Palo Alto CA
John Peter Herz - Los Altos CA
Mitchell Allen Altman - San Francisco CA
William Edward Smith - Hayward CA
John Peter Herz - Los Altos CA
Mitchell Allen Altman - San Francisco CA
William Edward Smith - Hayward CA
Assignee:
3ware, Inc. - Palo Alto CA
International Classification:
G06F 1314
US Classification:
710 5
Abstract:
A high-performance RAID system for a PC comprises a controller card which controls an array of ATA disk drives. The controller card includes an array of automated disk drive controllers, each of which controls one respective disk drive. The disk drive controllers are connected to a microcontroller by a control bus and are connected to an automated coprocessor by a packet-switched bus. The coprocessor accesses system memory and a local buffer. In operation, the disk drive controllers respond to controller commands from the microcontroller by accessing their respective disk drives, and by sending packets to the coprocessor over the packet-switched bus. The packets carry I/O data (in both directions, with the coprocessor filling-in packet payloads on I/O writes), and carry transfer commands and target addresses that are used by the coprocessor to access the buffer and system memory. The packets also carry special completion values (generated by the microcontroller) and I/O request identifiers that are processed by a logic circuit of the coprocessor to detect the completion of processing of each I/O request. The coprocessor grants the packet-switched bus to the disk drive controllers using a round robin arbitration protocol which guarantees a minimum I/O bandwidth to each disk drive.
Disk Array System For Processing And Tracking The Completion Of I/O Requests
US Patent:
6098114, Aug 1, 2000
Filed:
Mar 4, 1998
Appl. No.:
9/034812
Inventors:
James Arthur McDonald - Palo Alto CA
John Peter Herz - Los Altos CA
Mitchell Allen Altman - San Francisco CA
William Edward Smith - Hayward CA
John Peter Herz - Los Altos CA
Mitchell Allen Altman - San Francisco CA
William Edward Smith - Hayward CA
Assignee:
3Ware - Palo Alto CA
International Classification:
G06F 1314
US Classification:
710 5
Abstract:
A high-performance RAID system for a PC comprises a controller card which controls an array of ATA disk drives. The controller card includes an array of automated disk drive controllers, each of which controls one respective disk drive. The disk drive controllers are connected to a microcontroller by a control bus and are connected to an automated coprocessor by a packet-switched bus. The coprocessor accesses system memory and a local buffer. In operation, the disk drive controllers respond to controller commands from the microcontroller by accessing their respective disk drives, and by sending packets to the coprocessor over the packet-switched bus. The packets carry I/O data (in both directions, with the coprocessor filling-in packet payloads on I/O writes), and carry transfer commands and target addresses that are used by the coprocessor to access the buffer and system memory. The packets also carry special completion values (generated by the microcontroller) and I/O request identifiers that are processed by a logic circuit of the coprocessor to detect the completion of processing of each I/O request. The coprocessor grants the packet-switched bus to the disk drive controllers using a round robin arbitration protocol which guarantees a minimum I/O bandwidth to each disk drive.
High-Performance Bus Architecture For Disk Array System
US Patent:
6134630, Oct 17, 2000
Filed:
Mar 4, 1998
Appl. No.:
9/034247
Inventors:
James Arthur McDonald - Palo Alto CA
John Peter Herz - Los Altos CA
Mitchell Allen Altman - San Francisco CA
William Edward Smith - Hayward CA
John Peter Herz - Los Altos CA
Mitchell Allen Altman - San Francisco CA
William Edward Smith - Hayward CA
Assignee:
3Ware - Palo Alto CA
International Classification:
G06F 1200
US Classification:
711114
Abstract:
A high-performance RAID system for a PC comprises a controller card which controls an array of ATA disk drives. The controller card includes an array of automated disk drive controllers, each of which controls one respective disk drive. The disk drive controllers are connected to a microcontroller by a control bus and are connected to an automated coprocessor by a packet-switched bus. The coprocessor accesses system memory and a local buffer. In operation, the disk drive controllers respond to controller commands from the microcontroller by accessing their respective disk drives, and by sending packets to the coprocessor over the packet-switched bus. The packets carry I/O data (in both directions, with the coprocessor filling-in packet payloads on I/O writes), and carry transfer commands and target addresses that are used by the coprocessor to access the buffer and system memory. The packets also carry special completion values (generated by the microcontroller) and I/O request identifiers that are processed by a logic circuit of the coprocessor to detect the completion of processing of each I/O request. The coprocessor grants the packet-switched bus to the disk drive controllers using a round robin arbitration protocol which guarantees a minimum I/O bandwidth to each disk drive.
Memory Card Magazine System
US Patent:
7445156, Nov 4, 2008
Filed:
Oct 3, 2006
Appl. No.:
11/542795
Inventors:
James A. McDonald - Palo Alto CA, US
International Classification:
G06K 7/00
US Classification:
235486, 235451, 235482, 235492, 235495, 361796, 361797, 361798, 361799, 361800, 361801, 361802, 361803, 361737, 361752, 439 61, 439 65, 439630, 439631
Abstract:
A data management device and library are provided for organizing, holding, and providing electrical connectivity to multiple memory cards. The data management device can comprise a device body, a plurality of sockets to accommodate the data storage media, an electrical connector, and a power management circuit. Data can be retrieved from or transferred to the selected memory cards utilizing the device. The data management library can be utilized to interconnect multiple devices and can be daisy chained to other libraries.
Disk Drive Data Protection Using Clusters Containing Error Detection Sectors
US Patent:
2004016, Aug 26, 2004
Filed:
Feb 6, 2004
Appl. No.:
10/774164
Inventors:
Richard Biskup - Sunnyvale CA, US
Brian Davis - Sunnyvale CA, US
James McDonald - Palo Alto CA, US
Robert Horst - Saratoga CA, US
Brian Davis - Sunnyvale CA, US
James McDonald - Palo Alto CA, US
Robert Horst - Saratoga CA, US
International Classification:
H02H003/05
US Classification:
714/008000
Abstract:
The present invention is related to methods and apparatus that can enhance the reliability of a hard drive by providing a built-in error check in the drive. Conventional hard drives can erroneously seek to an incorrect location on a platter of the hard drive. The erroneous seek corrupts the data stream and is difficult to detect and correct. Embodiments of the present invention can detect a logical block address assigned to a portion of the platter of the hard drive and thereby detect when an erroneous seek has occurred. Upon detection of an error, one embodiment of the present invention can further take corrective action to read from the correct portion of the platter.