DR. JAMES ALAN CHAMBERS, M.D., M.P.H.
Radiology at Riveredge Dr, Plano, TX

License number
Texas 01047879A
Category
Radiology
Type
Surgery
Address
Address
6400 Riveredge Dr, Plano, TX 75024
Phone
(972) 624-8188

Personal information

See more information about JAMES ALAN CHAMBERS at radaris.com
Name
Address
Phone
James Chambers, age 77
455 Skyline Rd, Dale, TX 78616
(512) 243-3401
James Chambers
4606 Connelly St, Austin, TX 78751
(512) 245-2799
James Chambers, age 44
4610 Madrid Dr, Georgetown, TX 78628
James Chambers
5716 Sterling Green Trl, Arlington, TX 76017
James Chambers, age 88
5714 Dan Duryea St, San Antonio, TX 78240
(210) 684-0221

Professional information

See more information about JAMES ALAN CHAMBERS at trustoria.com
James Chambers Photo 1
Method For The Selective Removal Of High-K Dielectrics

Method For The Selective Removal Of High-K Dielectrics

US Patent:
6656852, Dec 2, 2003
Filed:
Dec 6, 2001
Appl. No.:
10/006081
Inventors:
Antonio Luis Pacheco Rotondaro - Dallas TX
James Joseph Chambers - Plano TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 21302
US Classification:
438749, 438745, 438287, 134 13
Abstract:
One aspect of the invention relates to a method of etching a high-k dielectric. The method involves removing an exposed portion of a high-k dielectric layer from a substrate by wet etching with a solution comprising water, a strong acid, an oxidizing agent, and a fluorine compound. The etching solution provides selectivity towards the high-k film against insulating materials and polysilicon and is therefore useful in manufacturing FETs.


James Chambers Photo 2
Method For Annealing Ultra-Thin, High Quality Gate Oxide Layers Using Oxidizer/Hydrogen Mixtures

Method For Annealing Ultra-Thin, High Quality Gate Oxide Layers Using Oxidizer/Hydrogen Mixtures

US Patent:
6780719, Aug 24, 2004
Filed:
Jun 20, 2001
Appl. No.:
09/885744
Inventors:
Hiroaki Niimi - Richardson TX
Rajesh Khamankar - Coppell TX
James J. Chambers - Plano TX
Sunil Hattangady - McKinney TX
Antonio L. P. Rotondaro - Dallas TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 21336
US Classification:
438287, 438762, 438763, 438775, 438776, 438777
Abstract:
An embodiment of the present invention is a method of forming an ultra-thin dielectric layer, the method comprising the steps of: providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposing the oxygen-containing layer to a nitrogen-containing plasma to create a uniform nitrogen distribution throughout the oxygen-containing layer; and re-oxidizing and annealing the layer to stabilize the nitrogen distribution, heal plasma-induced damage, and reduce interfacial defect density. This annealing step is selected from a group of four re-oxidizing techniques: Consecutive annealing in a mixture of H2 and N2 (preferably less than 20% H2), and then a mixture of O2 and N2 (preferably less than 20% O2); annealing by a spike-like temperature rise (preferably less than 1 s at 1000 to 1150° C. ) in nitrogen-comprising atmosphere (preferably N2/O2 or N2O/H2); annealing by rapid thermal heating in ammonia of reduced pressure (preferably at 600 to 1000° C. for 5 to 60 s); annealing in an oxidizer/hydrogen mixture (preferably N2O with 1% H2) for 5 to 60 s at 800 to 1050° C.


James Chambers Photo 3
High Dielectric Constant Metal Silicates Formed By Controlled Metal-Surface Reactions

High Dielectric Constant Metal Silicates Formed By Controlled Metal-Surface Reactions

US Patent:
6521911, Feb 18, 2003
Filed:
Jul 19, 2001
Appl. No.:
09/908766
Inventors:
Gregory N. Parsons - Raleigh NC
James J. Chambers - Plano TX
M. Jason Kelly - Raleigh NC
Assignee:
North Carolina State University - Raleigh NC
International Classification:
H01L 2904
US Classification:
257 52, 438482
Abstract:
A method of forming an insulation layer on a semiconductor substrate includes modifying a surface of a semiconductor substrate with a metal or a metal-containing compound and oxygen to form an insulation layer on the surface of the semiconductor substrate, wherein the insulation layer comprises the metal or metal-containing compound, oxygen, and silicon such that the dielectric constant of the insulation layer is greater relative to an insulation layer formed of silicon dioxide, and wherein the insulation layer comprises metal-oxygen-silicon bonds.


James Chambers Photo 4
Temperature Spike For Uniform Nitridization Of Ultra-Thin Silicon Dioxide Layers In Transistor Gates

Temperature Spike For Uniform Nitridization Of Ultra-Thin Silicon Dioxide Layers In Transistor Gates

US Patent:
6503846, Jan 7, 2003
Filed:
Jun 20, 2001
Appl. No.:
09/885587
Inventors:
Hiroaki Niimi - Richardson TX
James J. Chambers - Plano TX
Rajesh Khamankar - Coppell TX
Douglas T. Grider - McKinney TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 2131
US Classification:
438776, 438513, 438775, 438792
Abstract:
An embodiment of the present invention is a method of forming an ultra-thin dielectric layer, the method comprising the steps of: providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposing the oxygen-containing layer to a nitrogen-containing plasma to create a uniform nitrogen distribution throughout the oxygen-containing layer; and re-oxidizing and annealing the layer to stabilize the nitrogen distribution, heal plasma-induced damage, and reduce interfacial defect density. This annealing step is selected from a group of four re-oxidizing techniques: Consecutive annealing in a mixture of H2 and N2 (preferably less than 20% H2), and then a mixture of O2 and N2 (preferably less than 20% O2); annealing by a spike-like temperature rise (preferably less than 1 s at 1000 to 1150° C. ) in nitrogen-comprising atmosphere (preferably N2/O2 or N2O/H2); annealing by rapid thermal heating in ammonia of reduced pressure (preferably at 600 to 1000° C. for 5 to 60 s); annealing in an oxidizer/hydrogen mixture (preferably N2O with 1% H2) for 5 to 60 s at 800 to 1050° C.


James Chambers Photo 5
Reliable High Voltage Gate Dielectric Layers Using A Dual Nitridation Process

Reliable High Voltage Gate Dielectric Layers Using A Dual Nitridation Process

US Patent:
7183165, Feb 27, 2007
Filed:
Nov 6, 2003
Appl. No.:
10/702234
Inventors:
Rajesh Khamankar - Coppell TX, US
Douglas T. Grider - McKinney TX, US
Hiroaki Niimi - Richardson TX, US
April Gurba - Plano TX, US
Toan Tran - Rowlett TX, US
James J. Chambers - Plano TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 21/336
US Classification:
438287, 257500
Abstract:
Dual gate dielectric layers are formed on a semiconductor substrate for MOS transistor fabrication. A first dielectric layer () is formed on a semiconductor substrate (). A first plasma nitridation process is performed on said first dielectric layer. The first dielectric layer () is removed in regions of the substrate and a second dielectric layer () is formed in these regions. A second plasma nitridation process is performed on the first dielectric layer and the second dielectric layer. MOS transistors () are then fabricated using the dielectric layers ().