JACK CORNELES WYBENGA
Pilots at Stone Crk Dr, Plano, TX

License number
Texas A2111091
Issued Date
Dec 2016
Expiration Date
Dec 2018
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
2129 Stone Creek Dr, Plano, TX 75075

Professional information

Jack Wybenga Photo 1

Apparatus And Method For Sharing Variables And Resources In A Multiprocessor Routing Node

US Patent:
7733857, Jun 8, 2010
Filed:
Dec 17, 2004
Appl. No.:
11/015738
Inventors:
Jack C. Wybenga - Plano TX, US
Patricia K. Sturm - Marion IA, US
Yingwei Wang - Dallas TX, US
Assignee:
Samsung Electronics Co., Ltd. - Suwon-si
International Classification:
H04L 12/28, H04L 12/56
US Classification:
370389
Abstract:
A router for transferring data packets between external devices. The router comprises: 1) a switch fabric; and 2) R routing nodes coupled to the switch fabric. Each routing node exchanges data packets with the external devices and with other routing nodes via the switch fabric. A first routing node comprises: i) an inbound network processor comprising a first plurality of microengines capable of forwarding incoming data packets from external ports to the switch fabric; ii) an outbound network processor comprising a second plurality of microengines capable of forwarding outgoing data packets from the switch fabric to the external ports; and iii) an asynchronous variables circuit for controlling access of the inbound and outbound network processors to at least one of i) a shared resource and ii) a shared variable in the router.


Jack Wybenga Photo 2

Apparatus And Method For Route Summarization And Distribution In A Massively Parallel Router

US Patent:
7369561, May 6, 2008
Filed:
Apr 26, 2004
Appl. No.:
10/832010
Inventors:
Jack C. Wybenga - Plano TX, US
Patricia K. Sturm - McKinney TX, US
Jorge Fossati - Plano TX, US
Assignee:
Samsung Electronics Co., Ltd. - Suwon-si
International Classification:
H04L 12/28, H04L 12/56, H04L 12/26, G06F 15/173
US Classification:
370396, 370238, 709242
Abstract:
A router for interconnecting external devices coupled to the router. The router comprises a switch fabric and a plurality of routing nodes coupled to the switch fabric. Each routing node is capable of transmitting data packets to, and receiving data packets from, the external devices and is further capable of transmitting data packets to, and receiving data packets from, other routing nodes via the switch fabric. The router also comprises a control processor for comparing the N most significant bits of a first subnet address associated with a first external port of a first routing node with the N most significant bits of a second subnet address associated with a second external port of the first routing node. The router determines a P-bit prefix of similar leading bits in the first and second subnet addresses and transmits the P-bit prefix to other routing nodes.


Jack Wybenga Photo 3

Apparatus And Method For Route Summarization And Distribution In A Massively Parallel Router

US Patent:
7782874, Aug 24, 2010
Filed:
Feb 19, 2008
Appl. No.:
12/070549
Inventors:
Jack C. Wybenga - Plano TX, US
Patricia Kay Sturm - McKinney TX, US
Jorge Fossati - Plano TX, US
Assignee:
Samsung Electronics Co., Ltd. - Suwon-si
International Classification:
H04L 12/28, H04L 12/56, H04L 1/00, H04L 12/26, G06F 15/173
US Classification:
370396, 370238, 709242
Abstract:
A router for interconnecting external devices coupled to the router. The router comprises a switch fabric and a plurality of routing nodes coupled to the switch fabric. Each routing node is capable of transmitting data packets to, and receiving data packets from, the external devices and is further capable of transmitting data packets to, and receiving data packets from, other routing nodes via the switch fabric. The router also comprises a control processor for comparing the N most significant bits of a first subnet address associated with a first external port of a first routing node with the N most significant bits of a second subnet address associated with a second external port of the first routing node. The router determines a P-bit prefix of similar leading bits in the first and second subnet addresses and transmits the P-bit prefix to other routing nodes.


Jack Wybenga Photo 4

Distribution Of Operating System Functions For Increased Data Processing Performance In A Multi-Processor Architecture

US Patent:
2005027, Dec 15, 2005
Filed:
Mar 28, 2005
Appl. No.:
11/091362
Inventors:
Jack Wybenga - Plano TX, US
Patricia Sturm - Marion IA, US
William Farris - Richardson TX, US
Assignee:
SAMSUNG ELECTRONICS CO., LTD. - Suwon-city
International Classification:
G06F009/46
US Classification:
718100000
Abstract:
An accelerated operating system can increase the data processing throughput of a data processor executing an application according to a sequential programming model. An application running on a main data processor is interfaced to an operating system which has been accelerated by distributing at least some of the operating system among a plurality of subordinate data processors which provide data processing support for the application running on the main data processor. The subordinate data processors can thus also provide operating system support for the application running on the main data processor. This decreases the processing burden on the main data processor, thereby increasing the main data processor's data processing throughput while executing the application.


Jack Wybenga Photo 5

Apparatus And Method For Forwarding Mixed Data Packet Types In A High-Speed Router

US Patent:
7440460, Oct 21, 2008
Filed:
Mar 5, 2004
Appl. No.:
10/794506
Inventors:
Jack C. Wybenga - Plano TX, US
Patrick W. Ireland - Sanger TX, US
Patricia K. Sturm - McKinney TX, US
Assignee:
Samsung Electronics Co., Ltd. - Suwon-si
International Classification:
H04L 12/28, H04L 12/54
US Classification:
37039531, 370428
Abstract:
A routing table search circuit comprising a forwarding table containing forwarding table entries, each forwarding table entry comprising a destination address, and a content addressable memory (CAM) comprising a CAM lookup table, the CAM receiving a search key and outputting a CAM search result corresponding to the search key from the CAM lookup table. The search key comprises at least: i) a packet type field associated with the first received address and ii) an address field containing a most significant bits portion of the first received address. The routing table search circuit also comprises M pipelined memory stages for storing a trie table that translates the first received address into the first destination address. The M pipelined memory stages are searched using the CAM search result and a remaining bits portion of the first received address. Each of the M pipelined memory stages outputs a stage search result.


Jack Wybenga Photo 6

Apparatus And Method For Distributing Control Plane Functions In A Multiprocessor Router

US Patent:
7471676, Dec 30, 2008
Filed:
Apr 16, 2004
Appl. No.:
10/826138
Inventors:
Jack C. Wybenga - Plano TX, US
Patrick W. Ireland - Sanger TX, US
Patricia Kay Sturm - McKinney TX, US
Assignee:
Samsung Electronics Co., Ltd. - Suwon-si
International Classification:
H04L 12/28, H04L 12/56
US Classification:
370389, 370400, 370419
Abstract:
A router for interconnecting external devices. The router comprises a switch fabric and a plurality of routing nodes coupled to the switch fabric. Each routing node comprises packet processing circuitry for transmitting data packets to, and receiving data packets from, the external devices and for transmitting data packets to, and receiving data packets from, other routing nodes via the switch fabric and control data processing circuitry capable of performing control and management functions. The control data processing circuitry comprises a first network processor for performing control and management functions associated with the router and a second network processor for performing control and management functions associated with the router. The control and management functions are dynamically allocated between the first network processor and the second network processor.


Jack Wybenga Photo 7

Apparatus And Method Using Vector Table Indirection To Maintain Forwarding Tables In A Router

US Patent:
7567571, Jul 28, 2009
Filed:
Dec 17, 2004
Appl. No.:
11/015750
Inventors:
Jack C. Wybenga - Plano TX, US
Patricia K. Sturm - Marion IA, US
Patrick W. Ireland - Sanger TX, US
Assignee:
Samsung Electronics Co., Ltd. - Suwon-si
International Classification:
H04L 12/28, H04L 12/56
US Classification:
37039532
Abstract:
A router for interconnecting external devices comprising: 1) a switch fabric; and 2) R routing nodes coupled to the switch fabric. Each of the R routing nodes exchanges data packets with the external devices via network interface ports and with other routing nodes via the switch fabric. A first routing node comprises: i) an inbound network processor for receiving incoming data packets from a network interface port; ii) an outbound network processor for transmitting data packets to the network interface port; and iii) a shared memory accessible by the inbound and outbound network processors for storing a current trie tree search table and a current vector table used to index into the trie tree search table. A control plane processor generates an updated vector table to replace the current vector table and notifies the inbound and outbound network processors that the updated vector table is available.


Jack Wybenga Photo 8

Apparatus And Method For Architecturally Redundant Ethernet

US Patent:
7787385, Aug 31, 2010
Filed:
Jan 25, 2005
Appl. No.:
11/043021
Inventors:
Jack C. Wybenga - Plano TX, US
Patricia Kay Sturm - Marion IA, US
Steven Eugene Tharp - Garland TX, US
Assignee:
Samsung Electronics Co., Ltd. - Suwon-si
International Classification:
H04L 12/26, H04J 1/00
US Classification:
370242, 370216, 370230, 370484
Abstract:
A routing apparatus comprising: 1) a first router coupled to a first plurality of Ethernet links; and 2) a second router coupled to a second plurality of Ethernet links, wherein selected ones of the first plurality of Ethernet links are coupled to selected ones of the second plurality of Ethernet links to thereby form Ethernet trunk groups in which traffic associated with a plurality of Ethernet ports are aggregated into a single logical port. The routing apparatus further comprises a first high-speed link and a second high-speed link directly coupling the first router and the second router and forming a self-healing ring for transferring data packets between the first and second routers. In response to a failure associated with the failing one of the first and second routers, the first and second high-speed links transfer data traffic from the failing router to the non-failing router.


Jack Wybenga Photo 9

Apparatus And Method For Managing Traffic And Quality Of Service In A High-Speed Router

US Patent:
2005018, Aug 25, 2005
Filed:
Feb 20, 2004
Appl. No.:
10/783936
Inventors:
Jack Wybenga - Plano TX, US
Steven Tharp - Gerland TX, US
Patricia Sturm - McKinney TX, US
Assignee:
SAMSUNG ELECTRONICS CO., LTD. - Suwon-city
International Classification:
H04L012/56
US Classification:
370230000
Abstract:
A router for interconnecting external devices coupled to the router. The router comprises a switch fabric and a plurality of routing nodes coupled to the switch fabric. Each of the routing nodes transmits data packets to, and receives data packets from, the external devices and other routing nodes via the switch fabric. The switch fabric detects that the output bandwidth of a first output of the switch fabric has been exceeded and, in response to the detection, attempts to slow the input ports and drops lower priority packets if necessary. The routing nodes give precedence to routing higher priority packets.


Jack Wybenga Photo 10

Apparatus And Method For Workflow-Based Routing In A Distributed Architecture Router

US Patent:
7564860, Jul 21, 2009
Filed:
May 8, 2003
Appl. No.:
10/431774
Inventors:
Jack C. Wybenga - Plano TX, US
Patricia K. Sturm - Dallas TX, US
Assignee:
Samsung Electronics Co., Ltd. - Suwon-si
International Classification:
H04L 12/56
US Classification:
370420
Abstract:
A router for transmitting data packets to and receiving data packets from N interfacing peripheral devices. The router comprises a plurality of processors that exchange data packets with each other over a common bus. A source processor transmits a data packet to a destination processor by storing the data packet in an output queue associated with the source processor and transmits an interrupt message to the destination processor. The destination processor, in response to the interrupt message, reads the data packet from the output queue.