IRENE LIN
Marriage and Family Therapists at Distel Cir, Los Altos, CA
License number
California A64706
Category
Osteopathic Medicine
Type
Family Medicine
Address
Address
2
370 Distel Cir, Los Altos, CA 94022
PO Box 10000, Palo Alto, CA 94303
PO Box 10000, Palo Alto, CA 94303
Phone
(650) 254-5200
Professional information
Dr. Irene Lin, Los Altos CA - MD (Doctor of Medicine)
Specialties:
Family Medicine
Address:
Palo Alto Medical Foundation
370 Distel Cir, Los Altos 94022
(650) 254-5200 (Phone)
370 Distel Cir, Los Altos 94022
(650) 254-5200 (Phone)
Certifications:
Family Practice, 2005
Awards:
Healthgrades Honor Roll
Languages:
English, Spanish
Hospitals:
Palo Alto Medical Foundation
370 Distel Cir, Los Altos 94022
Sequoia Hospital
170 Alameda De Las Pulgas, Redwood City 94062
Stanford Hospital and Clinics
300 Pasteur Dr, Stanford 94305
Washington Hospital
2000 Mowry Ave, Fremont 94538
370 Distel Cir, Los Altos 94022
Sequoia Hospital
170 Alameda De Las Pulgas, Redwood City 94062
Stanford Hospital and Clinics
300 Pasteur Dr, Stanford 94305
Washington Hospital
2000 Mowry Ave, Fremont 94538
Education:
Medical School
Stanford University School Of Medicine
Graduated: 1996
Stanford University School Of Medicine
Graduated: 1996
Irene Iwasaki Lin, Los Altos CA
Specialties:
Family Medicine
Work:
Los Altos Center
370 Distel Cir, Los Altos, CA 94022
370 Distel Cir, Los Altos, CA 94022
Education:
Stanford University (1996)
Irene Lin, Los Altos CA
Specialties:
Family Physician
Address:
370 Distel Cir, Los Altos, CA 94022
Semiconductor Devices Formed On A Continuous Active Region With An Isolating Conductive Structure Positioned Between Such Semiconductor Devices, And Methods Of Making Same
US Patent:
8618607, Dec 31, 2013
Filed:
Jul 2, 2012
Appl. No.:
13/539830
Inventors:
Mahbub Rashed - Santa Clara CA, US
David Doman - Austin TX, US
Marc Tarabbia - Pleasant Valley NY, US
Irene Lin - Los Altos Hills CA, US
Jeff Kim - San Jose CA, US
Chinh Nguyen - Austin TX, US
Steve Soss - Cornwall NY, US
Scott Johnson - Wappingers Falls NY, US
Subramani Kengeri - San Jose CA, US
Suresh Venkatesan - Malta NY, US
David Doman - Austin TX, US
Marc Tarabbia - Pleasant Valley NY, US
Irene Lin - Los Altos Hills CA, US
Jeff Kim - San Jose CA, US
Chinh Nguyen - Austin TX, US
Steve Soss - Cornwall NY, US
Scott Johnson - Wappingers Falls NY, US
Subramani Kengeri - San Jose CA, US
Suresh Venkatesan - Malta NY, US
Assignee:
GLOBALFOUNDRIES Inc. - Grand Cayman
International Classification:
H01L 21/02
US Classification:
257359, 257369, 257379, 257E21602, 257E21656, 257E23144, 257E23152, 257E27029, 257E27081, 257E29226, 257E29276
Abstract:
One illustrative device disclosed herein includes a continuous active region defined in a semiconducting substrate, first and second transistors formed in and above the continuous active region, each of the first and second transistors comprising a plurality of doped regions formed in the continuous active region, a conductive isolating electrode positioned above the continuous active region between the first and second transistors and a power rail conductively coupled to the conductive isolating electrode.
Middle-Of-The-Line Constructs Using Diffusion Contact Structures
US Patent:
2014004, Feb 13, 2014
Filed:
Aug 7, 2012
Appl. No.:
13/568737
Inventors:
Mahbub Rashed - Santa Clara CA, US
Yuansheng Ma - Santa Clara CA, US
Irene Lin - Los Altos Hills CA, US
Jason Stephens - Beacon NY, US
Yunfei Deng - Sunnyvale CA, US
Yuan Lei - Sunnyvale CA, US
Jongwook Kye - Pleasanton CA, US
Rod Augur - Hopewell Junction NY, US
Shibly Ahmed - San Jose CA, US
Subramani Kengeri - San Jose CA, US
Suresh Venkatesan - San Jose CA, US
Yuansheng Ma - Santa Clara CA, US
Irene Lin - Los Altos Hills CA, US
Jason Stephens - Beacon NY, US
Yunfei Deng - Sunnyvale CA, US
Yuan Lei - Sunnyvale CA, US
Jongwook Kye - Pleasanton CA, US
Rod Augur - Hopewell Junction NY, US
Shibly Ahmed - San Jose CA, US
Subramani Kengeri - San Jose CA, US
Suresh Venkatesan - San Jose CA, US
Assignee:
GLOBALFOUNDRIES INC. - Grand Cayman
International Classification:
H01L 21/768, H01L 23/48
US Classification:
257775, 438586, 257E23011, 257E2159
Abstract:
An approach for providing MOL constructs using diffusion contact structures is disclosed. Embodiments include: providing a first diffusion region in a substrate; providing, via a first lithography process, a first diffusion contact structure; providing, via a second lithography process, a second diffusion contact structure; and coupling the first diffusion contact structure to the first diffusion region and the second diffusion contact structure. Embodiments include: providing a second diffusion region in the substrate; providing a diffusion gap region between the first and second diffusion regions; providing the diffusion contact structure over the diffusion gap region; and coupling, via the diffusion contact structure, the first and second diffusion regions.
Semiconductor Device With Transistor Local Interconnects
US Patent:
8581348, Nov 12, 2013
Filed:
Dec 13, 2011
Appl. No.:
13/324699
Inventors:
Mahbub Rashed - Santa Clara CA, US
Steven Soss - Cornwall NY, US
Jongwook Kye - Pleasanton CA, US
Irene Y. Lin - Los Altos Hills CA, US
James Benjamin Gullette - Wadesboro NC, US
Chinh Nguyen - Austin TX, US
Jeff Kim - San Jose CA, US
Marc Tarabbia - Pleasant Valley NY, US
Yuansheng Ma - Santa Clara CA, US
Yunfei Deng - Sunnyvale CA, US
Rod Augur - Hopewell Junction NY, US
Seung-Hyun Rhee - Fishkill NY, US
Scott Johnson - Wappingers Falls NY, US
Subramani Kengeri - San Jose CA, US
Suresh Venkatesan - Danbury CT, US
Steven Soss - Cornwall NY, US
Jongwook Kye - Pleasanton CA, US
Irene Y. Lin - Los Altos Hills CA, US
James Benjamin Gullette - Wadesboro NC, US
Chinh Nguyen - Austin TX, US
Jeff Kim - San Jose CA, US
Marc Tarabbia - Pleasant Valley NY, US
Yuansheng Ma - Santa Clara CA, US
Yunfei Deng - Sunnyvale CA, US
Rod Augur - Hopewell Junction NY, US
Seung-Hyun Rhee - Fishkill NY, US
Scott Johnson - Wappingers Falls NY, US
Subramani Kengeri - San Jose CA, US
Suresh Venkatesan - Danbury CT, US
Assignee:
GLOBALFOUNDRIES, Inc. - Grand Cayman
International Classification:
H01L 27/088, H01L 21/70, H01L 21/02
US Classification:
257401, 257368, 257369, 257382, 257384
Abstract:
A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors includes a source, a drain, and a gate. A CA layer is electrically connected to at least one of the source or the drain of the first transistor. A CB layer is electrically connected to at least one of the gates of the transistors and the CA layer.
Semiconductor Device With Transistor Local Interconnects
US Patent:
2013014, Jun 13, 2013
Filed:
Dec 13, 2011
Appl. No.:
13/324740
Inventors:
Mahbub Rashed - Santa Clara CA, US
Irene Y. Lin - Los Altos Hills CA, US
Steven Soss - Cornwall NY, US
Jeff Kim - San Jose CA, US
Chinh Nguyen - Austin TX, US
Marc Tarabbia - Pleasant Valley NY, US
Scott Johnson - Wappingers Falls NY, US
Subramani Kengeri - San Jose CA, US
Suresh Venkatesan - Danbury CT, US
Irene Y. Lin - Los Altos Hills CA, US
Steven Soss - Cornwall NY, US
Jeff Kim - San Jose CA, US
Chinh Nguyen - Austin TX, US
Marc Tarabbia - Pleasant Valley NY, US
Scott Johnson - Wappingers Falls NY, US
Subramani Kengeri - San Jose CA, US
Suresh Venkatesan - Danbury CT, US
International Classification:
H01L 27/092, H01L 27/088
US Classification:
257369, 257368, 257E27062, 257E2706
Abstract:
A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors comprises a source, a drain, and a gate. A trench silicide layer electrically connects one of the source or the drain of the first transistor to one of the source or the drain of the second transistor.
Semiconductor Device Having Contact Layer Providing Electrical Connections
US Patent:
8598633, Dec 3, 2013
Filed:
Jan 16, 2012
Appl. No.:
13/351101
Inventors:
Marc Tarabbia - Pleasant Valley NY, US
James B. Gullette - Dresden, DE
Mahbub Rashed - Santa Clara CA, US
David S. Doman - Austin TX, US
Irene Y. Lin - Los Altos Hills CA, US
Ingolf Lorenz - Ottendorf-Okrilla, DE
Larry Ho - Cupertino CA, US
Chinh Nguyen - Austin TX, US
Jeff Kim - San Jose CA, US
Jongwook Kye - Pleasanton CA, US
Yuansheng Ma - Santa Clara CA, US
Yunfei Deng - Sunnyvale CA, US
Rod Augur - Hopewell Junction NY, US
Seung-Hyun Rhee - Fishkill NY, US
Jason E. Stephens - Beacon NY, US
Scott Johnson - Wappingers Falls NY, US
Subramani Kengeri - San Jose CA, US
Suresh Venkatesan - Danbury CT, US
James B. Gullette - Dresden, DE
Mahbub Rashed - Santa Clara CA, US
David S. Doman - Austin TX, US
Irene Y. Lin - Los Altos Hills CA, US
Ingolf Lorenz - Ottendorf-Okrilla, DE
Larry Ho - Cupertino CA, US
Chinh Nguyen - Austin TX, US
Jeff Kim - San Jose CA, US
Jongwook Kye - Pleasanton CA, US
Yuansheng Ma - Santa Clara CA, US
Yunfei Deng - Sunnyvale CA, US
Rod Augur - Hopewell Junction NY, US
Seung-Hyun Rhee - Fishkill NY, US
Jason E. Stephens - Beacon NY, US
Scott Johnson - Wappingers Falls NY, US
Subramani Kengeri - San Jose CA, US
Suresh Venkatesan - Danbury CT, US
Assignee:
GLOBALFOUNDRIES, Inc. - Grand Cayman
International Classification:
H01L 23/52
US Classification:
257207, 257211
Abstract:
A semiconductor device includes a semiconductor substrate having a diffusion region. A transistor is formed within the diffusion region. A power rail is disposed outside the diffusion region. A contact layer is disposed above the substrate and below the power rail. A via is disposed between the contact layer and the power rail to electrically connect the contact layer to the power rail. The contact layer includes a first length disposed outside the diffusion region and a second length extending from the first length into the diffusion region and electrically connected to the transistor.