IN SUN KIM, L.AC.
Acupuncture at El Camino Real, Santa Clara, CA

6642758, Nov 4, 2003

Dec 5, 2000

09/731473

Bonnie I. Wang - Cupertino CA
Joseph Huang - San Jose CA
Chiakang Sung - Milpitas CA
Xiaobao Wang - Santa Clara CA
In Whan Kim - Santa Clara CA
Wayne Yeung - San Francisco CA
Khai Nguyen - San Jose CA

Altera Corporation - San Jose CA

H03L 7095

327156, 327159, 327160, 331 1 A, 331 17, 377119, 377120

A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit. In an implementation, the programmable phase shift circuitry is implemented using two programmable counters.

6292116, Sep 18, 2001

May 16, 2000

9/571766

Bonnie I. Wang - Cupertino CA
Chiakang Sung - Milpitas CA
In Whan Kim - Santa Clara CA
Wayne Yeung - San Francisco CA
Xiaobao Wang - Santa Clara CA
Khai Nguyen - San Jose CA
Joseph Huang - San Jose CA

Altera Corporation - San Jose CA

H03M 900

341100

Techniques and circuitry are provided to handle high frequency input data. The techniques and circuitry take a high-frequency serial input data stream and covert it into parallel form for handling within the integrated circuit. The circuitry ensures the high frequency data is strobed properly by accounting for skew between the high frequency data input and clock input. In an implementation, multiple clock strobes are generated having the same frequency but different phase. A predetermined series of bits is input to the high frequency input into the circuitry for training. One of the multiple clock strobes is selected based on which one correctly determines the bits in the predetermined input data stream. This clock strobe is selected to strobe the high frequency data input for the integrated circuit. In an embodiment, the high frequency data input is an LVDS input of a programmable logic integrated circuit.

6246270, Jun 12, 2001

Jul 1, 1999

9/345434

Bonnie Wang - Cupertino CA
Joseph Huang - San Jose CA
Wayne Yeung - San Francisco CA
Chiakang Sung - Milpitas CA
Richard Cliff - Los Altos CA
Khai Nguyen - San Jose CA
Xiaobao Wang - Santa Clara CA
In Whan Kim - Santa Clara CA

Altera Corporation - San Jose CA

H03K 426

327111

Disclosed is a current booster or kicker for an output amplifier of a programmable logic control or other integrated circuit. The current booster includes a control mechanism and an auxiliary voltage supply. When a change in output state is initiated, the control mechanism connects the auxiliary voltage supply to the output of the output amplifier. After a change in output state in completed, the control mechanism disconnects the auxiliary voltage supply from the output of the output amplifier. In this way, the output amplifier can drive a relatively high capacitance load at a relatively high slew rate.

7358783, Apr 15, 2008

Mar 25, 2003

10/400191

Bonnie I. Wang - Cupertino CA, US
Joseph Huang - San Jose CA, US
Chiakang Sung - Milpitas CA, US
Xiaobao Wang - Santa Clara CA, US
In Whan Kim - Santa Clara CA, US
Wayne Yeung - San Francisco CA, US
Khai Nguyen - San Jose CA, US

Altera Corporation - San Jose CA

H03L 7/095

327156, 327159, 327160

A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit. In an implementation, the programmable phase shift circuitry is implemented using two programmable counters.