Hyun Lee
Pharmacy in Allentown, PA

6611893, Aug 26, 2003

Dec 29, 1999

09/474411

Hyun Lee - Allentown PA
David W. Potter - Allentown PA

Agere Systems Inc. - Allentown PA

G06F 1336

710309

A method and apparatus for arbitrating access to a bus such that the bus can operate at a variable data rate, that rate being the rate of the slower of the two devices communicating over the bus. The smart arbiter in accordance with the invention has knowledge of the speed of the devices that use the bus and grants access in an order and at a rate based on that information. The smart arbiter can intersperse grants such that data transfers between multiple pairs of transmitting and receiving devices that are not independently utilizing the maximum bandwidth capabilities of the bus can overlap. Thus, if one pair of devices are exchanging multiple consecutive words (or other units of data) at a rate slower than the maximum rate of the bus, another pair of devices can use some of the bus clock cycles between the transfer of words of the first device pair, for transfers of words between the second device pair.

6725305, Apr 20, 2004

Dec 29, 1999

09/474412

Hyun Lee - Allentown PA
David W. Potter - Allentown PA
Lai Q. Pham - Center Valley PA

Agere Systems Inc. - Allentown PA

G06F 1300

710107

The present invention is a method and apparatus for dynamically holding valid data logic levels on a bus by taking advantage of the inherent storage capacity of the bus. The bus speed is increased by eliminating the use of active bus keepers and null cycles. Instead, a two phase clock is used, the bus drivers drive data onto the bus during the first phase of the clock and are turned off at the beginning of the second phase of the bus clock. The receiving device latches the data during the second phase of the bus clock. Accordingly, there is no need for a null cycle or a bus keeper circuit, yet there is no bus contention between consecutive drivers nor is there a floating node condition.

6622153, Sep 16, 2003

Jul 7, 1999

09/348447

Hyun Lee - Allentown PA
Shaun P. Whalen - Wescosville PA

Agere Systems, Inc. - Berkeley Heights NJ

G06F 738

708523

A virtual parallel multiplier-accumulator (VMAC) that can execute more than or less than one MAC operation in a single system clock cycle. The inventive VMAC advantageously employs a resource/time-sharing methodology with multiple sequential computational stages.

6108233, Aug 22, 2000

Aug 27, 1999

9/384346

Hyun Lee - Allentown PA
Mark Yeen Luong - Macungie PA

Lucent Technologies Inc. - Murray Hill NJ

G11C 1100

365154

An integrated circuit includes a memory cell that stores a data bit corresponding to one of a low and a high voltage. A memory element is coupled to a data node for storing the data bit and to an inverse data node for storing an inverse of the data bit. An access port of the memory cell comprises an access switch having a first terminal coupled to a data line, a second terminal coupled to the data node, and a control terminal coupled to an access control line which provides an access control signal for switching the access switch on or off to selectively couple the data line to the data node. The memory cell has a preset switch having a first terminal coupled to the inverse data node, a second terminal coupled to a logic-0 voltage source, and a preset control terminal coupled to a preset control line which provides a write preset control signal for switching the preset switch on or off to selectively couple the inverse data node to the logic-0 voltage source.

6175533, Jan 16, 2001

Apr 12, 1999

9/291158

Hyun Lee - Allentown PA
Mark Yeen Luong - Macungie PA

Lucent Technologies Inc. - Murray Hill NJ

G11C 800

36523005

An integrated circuit includes a memory cell that stores a data bit corresponding to one of a low and a high voltage. A memory element is coupled to a data node for storing the data bit and to an inverse data node for storing an inverse of the data bit. At least one write-access port has a write-access switch having an input terminal coupled to a data input line, an output terminal coupled to the data node, and a control terminal coupled to a write control line for switching the write-access switch on or off to provide a write-data bit from the data input line to the write-access port. A preset switch is employed which has a first terminal coupled to one of the data node and the inverse data node, a second terminal coupled to a voltage source sufficient to cause the data node to store a logic-1 data bit when the preset switch is on, and a preset control terminal for switching the preset switch on or off to preset the memory cell before a write operation is coupled to a preset control line.

5457414, Oct 10, 1995

Dec 22, 1992

7/994732

David A. Inglis - Long Branch NJ
Hyun Lee - Allentown PA

AT&T IPM Corp. - Coral Gables FL

H03K 5153, G05F 110

327 77

A clocked comparator circuit compares the primary and backup power supply voltages to a system. When the primary voltage falls a given amount below the backup, the circuit provides a signal that may be used to switch to the backup power supply. When the primary voltage is again present, the circuit can switch back to primary power. Alternatively, or additionally, a signal may be generated to initiate graceful shutdown of the system. The clock to the comparator typically operates at a higher frequency when operating on the primary voltage, and a lower frequency when operating on the backup voltage. This circuit is typically used with a portable system that uses a rechargeable battery as its primary power supply. The backup power supply may be a long-life battery that provides power to only a portion of the system. For example, in a computer, only a static memory may be powered by the backup, to allow the full system to retain its proper configuration when the primary power supply is again activated.

5289025, Feb 22, 1994

Oct 24, 1991

7/782034

Hyun Lee - Allentown PA

AT&T Bell Laboratories - Murray Hill NJ

H01L 2702, H01L 2978

257299

A wide variety of integrated circuit applications exist for boosted nodes, wherein a voltage is boosted above the power supply level. Typical uses include clock driver circuits in microprocessors, row lines in dynamic and static memory chips, and substrate bias generators. However, in the prior art, only n-channel transistors have been usable to boost nodes above the positive power supply level, to prevent forward-biasing the drain-to-substrate diode. The present invention allows a p-channel device source/drain region to be connected to a boosted node. This is accomplished by also boosting the voltage of the n-tub in which the device is formed, thereby allowing the p+ source/drain regions to be boosted without latch-up or other problems. Similarly, n-channel devices may be connected to nodes boosted more negative than V. sub. SS.

6282137, Aug 28, 2001

Sep 14, 1999

9/395835

Hyun Lee - Allentown PA
Michael J. Hunter - Mertztown PA

Agere Systems Guardian Corp. - Orlando FL

G11C 702

365207

The invention is a method and apparatus for minimizing voltage swing on the BIT and BIT lines of a static random access memory (SRAM), thus minimizing precharge time and READ time for the SRAM. In accordance with the invention, an enhanced sense amplifier is provided in the last column of the memory array. The enhanced sense amplifier detects when the differential voltage between the BIT and BIT lines exceeds the minimum detectable threshold of the sense amplifier. In response to that event, it asserts a feedback line to the READ control circuitry which halts the read operation essentially as soon as the differential voltage between the BIT and BIT lines reaches the minimum differential voltage detectable by the sense amplifier. The technique is adaptive and assures both accurate operation and minimal precharge and read access times across variations in temperature and other environmental conditions.

5416446, May 16, 1995

Dec 8, 1992

7/987917

Paul T. Holler - Allentown PA
Hyun Lee - Allentown PA

AT&T Corp. - Murray Hill NJ

H03B 524

331 57

Frequency generators that may be programmed are utilized in a wide variety of applications. Typical applications include radio and television receivers and transmitters, and computer devices that must operate at different clock rates, or be compatible with systems that operate at different clock rates. The present technique provides for programmably generating a frequency. A ring oscillator receives at least one operating voltage through a programmable array of field effect transistors. Digitally selecting a given set of the transistors provides a given operating current for the ring, which establishes the frequency of operation. In one embodiment, the technique is implemented in a CMOS integrated circuit. This technique provides for more rapid frequency changes in a low-power circuit than can be obtained with typical prior-art techniques (e. g. , a phase-locked loop).

7080113, Jul 18, 2006

Jul 17, 2003

10/622764

Hyun Lee - Allentown PA, US
Shaun P. Whalen - Wescosville PA, US

Agere Systems Inc. - Allentown PA

G06F 7/38

708523

A virtually parallel multiplier-accumulator (VMAC) that can execute more than or less than one MAC operation in a single system clock cycle. The inventive VMAC advantageously employs a resource/time-sharing methodology with multiple sequential computational stages.