Inventors:
Mark Layne Shaw - Austin TX
Howard Fredrick Weber - Scottsdale AZ
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G06M 302, G06M 308, B60K 3100
Abstract:
A digital speed control system includes a first binary up-counter called an Actual Count Register. The Actual Count Register is initially reset to contain all "0"'s. During a sample time, an input is applied to the Actual Count Register so that it counts up to a first binary number during the sample time. The first binary number represents a reference speed. The system includes a Reference Count Register. In response to read and store command, the first binary number is loaded into the Reference Count Register, where it remains until the next request for a new reference speed. The system further includes a first binary presettable up-counter called the Error Register. The Error Register counts up at the same rate and in response to the same count signal as the Actual Count Register. During a Transfer signal which follows the Read signal, the complement of the first binary number is transferred from the Reference Count Register into the Error Register. The system also includes a second binary presettable up-counter called an Acceleration Register.