Position:
MTS ASIC Design Verification Engineer at ATI/AMD
Work:
ATI/AMD
- Orlando, Florida Area since Jul 2010
-
MTS ASIC Design Verification Engineer
Intel
Sep 2009 - Apr 2010
-
Verification Engineer (Contract)
Texas Instruments
Sep 2006 - Jan 2009
-
Wireless EDA Methodology Engineer
Intel
Mar 2006 - Aug 2006
-
Verification Design Automation Engineer
Cadence Design Systems
Jul 2001 - Oct 2005
-
Lead PCB Product Validation Engineer
Education:
University of Florida 1999 - 2001
MS, Electrical and Computer Engineering
Shanghai Jiao Tong University 1994 - 1998
BS, Electrical Engineering