HONG CHANG
Nursing in Cupertino, CA

7932148, Apr 26, 2011

Feb 9, 2009

12/378040

Hong Chang - Cupertino CA, US
Tiesheng Li - San Jose CA, US
Yu Wang - Fremont CA, US

Alpha & Omega Semiconductor, Ltd

H01L 21/336

438259, 438283, 257340, 257E21002

This invention discloses an improved trenched metal oxide semiconductor field effect transistor (MOSFET) device that includes a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The MOSFET cell further includes a shielded gate trench (SGT) structure below and insulated from the trenched gate. The SGT structure is formed substantially as a round hole having a lateral expansion extended beyond the trench gate and covered by a dielectric liner layer filled with a trenched gate material. The round hole is formed by an isotropic etch at the bottom of the trenched gate and is insulated from the trenched gate by an oxide insulation layer. The round hole has a lateral expansion beyond the trench walls and the lateral expansion serves as a vertical alignment landmark for controlling the depth of the trenched gate. The MOSFET device has a reduced gate to drain capacitance Cgd depending on the controllable depth of the trenched gate disposed above the SGT structure formed as a round hole below the trenched gate.

7492005, Feb 17, 2009

Dec 28, 2005

11/321957

Hong Chang - Cupertino CA, US
Tiesheng Li - San Jose CA, US
Yu Wang - Fremont CA, US

Alpha & Omega Semiconductor, Ltd. - Hamilton

H01L 29/76

257330, 257340

This invention discloses an improved trenched metal oxide semiconductor field effect transistor (MOSFET) device that includes a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The MOSFET cell further includes a shielded gate trench (SGT) structure below and insulated from the trenched gate. The SGT structure is formed substantially as a round hole having a lateral expansion extended beyond the trench gate and covered by a dielectric liner layer filled with a trenched gate material. The round hole is formed by an isotropic etch at the bottom of the trenched gate and is insulated from the trenched gate by an oxide insulation layer. The round hole has a lateral expansion beyond the trench walls and the lateral expansion serves as a vertical alignment landmark for controlling the depth of the trenched gate. The MOSFET device has a reduced gate to drain capacitance Cgd depending on the controllable depth of the trenched gate disposed above the SGT structure formed as a round hole below the trenched gate.

8299494, Oct 30, 2012

Jun 12, 2009

12/484170

Hamza Yilmaz - Saratoga CA, US
Xiaobin Wang - San Jose CA, US
Anup Bhalla - Santa Clara CA, US
John Chen - Palo Alto CA, US
Hong Chang - Cupertino CA, US

Alpha & Omega Semiconductor, Inc. - Sunnyvale CA

H01L 29/74, H01L 31/111, H01L 29/76, H01L 29/94, H01L 31/062

257139, 257332, 257471, 257E29198, 257E29262

A semiconductor device includes a first semiconductor layer and a second semiconductor layer of opposite conductivity type, a first epitaxial layer of the first conductivity type formed on sidewalls of the trenches, and a second epitaxial layer of the second conductivity type formed on the first epitaxial layer where the second epitaxial layer is electrically connected to the second semiconductor layer. The first epitaxial layer and the second epitaxial layer form parallel doped regions along the sidewalls of the trenches, each having uniform doping concentration. The second epitaxial layer has a first thickness and a first doping concentration and the first epitaxial layer and a mesa of the first semiconductor layer together having a second thickness and a second average doping concentration where the first and second thicknesses and the first doping concentration and second average doping concentrations are selected to achieve charge balance in operation.

2007007, Apr 5, 2007

Sep 30, 2005

11/240255

Hong Chang - Cupertino CA, US
Tiesheng Li - San Jose CA, US
Daniel Ng - Campbell CA, US
Anup Bhalla - Santa Clara CA, US

H01L 29/78, H01L 21/336

257330000, 438270000, 438683000, 257384000

This invention discloses an improved trenched metal oxide semiconductor field effect transistor (MOSFET) cell that includes a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The MOSFET cell further includes a source contact opening opened on top of an area extended over the body region and the source region through a protective insulation layer wherein the area further has a cobalt-silicide layer disposed near a top surface of the substrate. The MOSFET cell further includes a Ti/TiN conductive layer covering the area interfacing with the cobalt-silicide layer over the source contact opening. The MOSFET cell further includes a source contact metal layer formed on top of the Ti/TiN conductive layer ready to form source-bonding wires thereon.

8431457, Apr 30, 2013

Mar 11, 2010

12/722384

Hong Chang - Cupertino CA, US
Yi Su - Sunnyvale CA, US
Wenjun Li - Shanghai, CN
Limin Weng - Shanghai, CN
Gary Chen - Shanghai, CN
Jongoh Kim - Suwon, KR
John Chen - Palo Alto CA, US

Alpha and Omega Semiconductor Incorporated - Sunnyvale CA

H01L 21/027, H01L 29/78

438270, 438259, 438430, 438431, 438432, 257330, 257333, 257334, 257E21585, 257E21655

A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device.

8598623, Dec 3, 2013

Sep 21, 2012

13/624066

Xiaobin Wang - San Jose CA, US
Anup Bhalla - Santa Clara CA, US
John Chen - Palo Alto CA, US
Hong Chang - Cupertino CA, US

Alpha and Omega Semiconductor Incorporated - Sunnyvale CA

H01L 29/74, H01L 31/111, H01L 29/76, H01L 29/94, H01L 31/062, H01L 21/332, H01L 21/336

257139, 257330, 257332, 257471, 257E21149, 257E21267, 257E29198, 257E29262, 438138, 438270

A termination structure for a semiconductor device includes an array of termination cells formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In other embodiments, semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches.

8008151, Aug 30, 2011

Nov 9, 2007

11/983769

Tiesheng Li - San Jose CA, US
Anup Bhalla - Santa Clara CA, US
Hong Chang - Cupertino CA, US
Moses Ho - Campbell CA, US

Alpha and Omega Semiconductor Limited

H01L 21/336

438259, 438270, 257E21655

A method of fabricating a semiconductor device comprises forming a hard mask on a substrate having a top substrate surface, forming a trench in the substrate, through the hard mask, depositing gate material in the trench, where the amount of gate material deposited in the trench extends beyond the top substrate surface, and removing the hard mask to leave a gate structure that extends substantially above the top substrate surface.

8247329, Aug 21, 2012

Feb 9, 2011

13/024256

Hamza Yilmaz - Saratoga CA, US
Xiaobin Wang - San Jose CA, US
Anup Bhalla - Santa Clara CA, US
John Chen - Palo Alto CA, US
Hong Chang - Cupertino CA, US

Alpha & Omega Semiconductor, Inc. - Sunnyvale CA

H01L 21/311

438700, 438197, 438510, 257E21042, 257E21043, 257E21051, 257E21077, 257E21267, 257E21404, 257E21435, 257E21545, 257E21546, 257E21562

A method for forming a semiconductor device includes forming a nanotube region using a thin epitaxial layer formed on the sidewall of a trench in the semiconductor body. The thin epitaxial layer has uniform doping concentration. In another embodiment, a first thin epitaxial layer of the same conductivity type as the semiconductor body is formed on the sidewall of a trench in the semiconductor body and a second thin epitaxial layer of the opposite conductivity type is formed on the first epitaxial layer. The first and second epitaxial layers have uniform doping concentration. The thickness and doping concentrations of the first and second epitaxial layers and the semiconductor body are selected to achieve charge balance. In one embodiment, the semiconductor body is a lightly doped P-type substrate. A vertical trench MOSFET, an IGBT, a Schottky diode and a P-N junction diode can be formed using the same N-Epi/P-Epi nanotube structure.

7632733, Dec 15, 2009

Apr 29, 2006

11/413248

Yu Wang - Fremont CA, US
Tiesheng Li - San Jose CA, US
Hong Chang - Cupertino CA, US

Alpha & Omega Semiconductor, Inc. - Sunnyvale CA

H01L 21/336

438270, 257E2153

This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining in a bottom portion in some of the trenches having smaller planar trench dimensions.

8053315, Nov 8, 2011

Oct 16, 2009

12/589045

Yong-Zhong Hu - Cupertino CA, US
François Hébert - San Mateo CA, US
Hong Chang - Cupertino CA, US
Mengyu Pan - Shanghai, CN
Yingying Lou - Shanghai, CN
Yu Wang - Fremont CA, US

Alpha & Omega Semiconductor, LTD

H01L 21/336

438270, 257E2141, 257E21419

This invention discloses a method of manufacturing a trenched semiconductor power device with split gate filling a trench opened in a semiconductor substrate wherein the split gate is separated by an inter-poly insulation layer disposed between a top and a bottom gate segments. The method further includes a step of forming the inter-poly layer by applying a RTP process after a HDP oxide deposition process to bring an etch rate of the HDP oxide layer close to an etch rate of a thermal oxide.