Hoang D Nguyen
Nail Technician at Pr Hl Dr, Fort Collins, CO

6002567, Dec 14, 1999

Oct 17, 1997

8/953184

ZhiYuan Zou - Fort Collins CO
Hoang P. Nguyen - Fort Collins CO

LSI Logic Corporation - Milpitas CA

H02H 322

361111

The present invention provides for ESD protection while allowing the use of an input signal that is higher than V. sub. DD. The present invention preferably includes a protection device and a delay circuit coupled to an input pad and to a ground reference. The protection device is a preferred silicon controlled rectifier, and the delay circuit is preferably a low pass filter RC circuit that includes a resistor and a capacitor. A node associated with the delay circuit is coupled to circuitry of an integrated circuit. The circuitry has associated therewith at least one gate oxide breakdown voltage. A gate oxide breakdown voltage is prevented from being applied to the circuitry of the integrated circuit. When an ESD voltage is applied to the input pad, the voltage at that pad ramps or increases quickly. The delay circuit prevents the node from ramping as quickly by delaying the ramping or increasing of the node voltage.

6515839, Feb 4, 2003

Mar 31, 1997

08/828246

Hoang P. Nguyen - Fort Collins CO 80526
John D. Walker - Colorado Springs CO 80907

H02H 320

361 915, 361111

An ESD protection system that makes use of several different types of over-voltage protection devices provides ESD conduction paths between different power lines. For example, the system may employ shunt diodes between the ground lines of the different power supplies and between IC pads and power supply lines; SCR protection between IC pads and ground; and thick field device protection between different power supply V lines. In this way, a conduction path for an ESD event between two circuit elements may be implemented using the device whose switching characteristics are best suited to that application.

5999029, Dec 7, 1999

Jun 28, 1996

8/671862

Hoang P. Nguyen - Fort Collins CO
Richard T. Schultz - Fort Collins CO

LSI Logic Corporation - Milpitas CA

H03K 3037

327198

A meta-hardened circuit that reduces the effects of metastability preferably includes a pulse generator coupled to receive a first clock signal and generate in response thereto a second clock signal and an enable signal. A buffer, preferably tri-state, is coupled to receive a first data signal and the enable signal and generate in response thereto a second data signal. A bi-stable device, such as a flip-flop, is coupled to receive the second clock signal and the second data signal. The pulse generator preferably includes a combining device and a delay device. The buffer preferably includes at least one tri-state inverter and a keeper circuit. A method to reduce the metastability effects preferably includes the step of generating a delay between a second data input signal and a second clock signal that is greater than a delay between a first data input signal and a first clock signal. The step of generating preferably occurs in one clock cycle. The method also preferably includes generating an enable pulse by generating a second clock signal in response to a first clock signal and combining the first and second clock signals to generate the enable signal, and generating a second data input signal in response to a first data input signal, where generating the second data input signal includes receiving an enable signal.

5616943, Apr 1, 1997

Jun 13, 1994

8/259240

Hoang P. Nguyen - Fort Collins CO
John D. Walker - Colorado Springs CO

AT&T Global Information Solutions Company - Dayton OH
Hyundai Electronics America - San Jose CA
Symbios Logic Inc. - Fort Collins CO

H01L 2362, H01L 2710

257355

An ESD protection system that makes use of several different types of over-voltage protection devices provides ESD conduction paths between different power lines. For example, the system may employ shunt diodes between the ground lines of the different power supplies and between I/O pads and power supply lines; SCR protection between I/O pads and ground; and thick field device protection between different power supply V. sub. DD lines. In this way, a conduction path for an ESD event between two input, output power and ground pads may be implemented using the device whose switching characteristics are best suited to that application.

5528447, Jun 18, 1996

Sep 30, 1994

8/315799

Michael J. McManus - Fort Collins CO
Philip W. Bullinger - Loveland CO
Andres R. Teene - Fort Collins CO
Gerald R. Haag - Fort Collins CO
Hoang P. Nguyen - Fort Collins CO

AT&T Global Information Solutions Company - Dayton OH
Hyundai Electronics America - Milpitas CA
Symbios Logic Inc. - Fort Collins CO

H02H 320

361 91

In an electronic IC package, an I/O PAD circuit design which protects 3 Volt optimized I/O functional circuits from damage due to the application of external 5 Volt signals to the I/O PAD both while the functional circuit design is powered on and powered off. When the I/O circuits associated with the I/O PAD are powered on, the present invention protects the I/O circuits by applying well known designs. However, when the I/O circuits associated with the I/O PAD are powered off, the present invention draws power from the external 5 Volt signal to activate additional transistors to protect the powered off I/O circuits.

5519355, May 21, 1996

Feb 14, 1995

8/389427

Hoang Nguyen - Fort Collins CO

AT&T Global Information Solutions Company - Dayton OH
Hyundai Electronics America - Milpitas CA
Symbios Logic Inc. - Fort Collins CO

H03K 1762, H01L 2500

327565

An input cell for a semiconductor chip having an I/O region proximate the edge of the chip and a core region located inside the I/O region. The input cell is located in the I/O region and includes an input pad for receiving an input signal and a multiplexer. The multiplexer receives an input signal from the pad or a boundary scan signal from the core region and selectively provides one signal or the other to the core region.