Inventors:
Patrick J. Smith - Houston TX
Jay B. Reimer - Houston TX
Ramesh A. Iyer - San Jose CA
Henry D. Nguyen - Houston TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G06F 1328
US Classification:
710 22, 710 23, 710 26, 710 48, 710 49, 710 52, 710308, 710309
Abstract:
In a data processing system including a plurality of digital signal processor subsystems, selected peripheral components are shared by the digital signal processor subsystems. In particular, the high level data link controller is shared by the subsystems. When a packet is received by a shared high level data link controller, the data signal groups are processed and placed in a temporary storage unit. The address signal group of the received packet is applied to channel block unit where the digital signal processor subsystem, to which the packet is directed, is identified and an INTERRUPT signal corresponding to the identified digital signal processor subsystem is generated. The INTERRUPT signal is applied to a switch. The switch, which receives the signal groups from the temporary storage unit, directs the signal groups to a buffer memory in the channel associated with the identified signal processing subsystem. In response to a predetermined condition, the signal groups are forwarded to the identified digital signal processor subsystem.